changeset 78f27ef5e919 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=78f27ef5e919
description:
ARM: Add support for initparam m5 op
diffstat:
configs/common/Options.py | 3 ++-
configs/example/fs.py | 3 +++
src/arch/arm/isa/insts/m5ops.isa | 8 +++++---
util/m5/m5.c | 16 ++++++++++++++--
4 files changed, 24 insertions(+), 6 deletions(-)
diffs (89 lines):
diff -r f1a69b7246f7 -r 78f27ef5e919 configs/common/Options.py
--- a/configs/common/Options.py Mon Jan 09 18:08:20 2012 -0600
+++ b/configs/common/Options.py Mon Jan 09 18:08:20 2012 -0600
@@ -63,7 +63,8 @@
help="exit at specified work end count")
parser.add_option("--work-begin-exit-count", action="store", type="int",
help="exit at specified work begin count")
-
+parser.add_option("--init-param", action="store", type="int", default=0,
+ help="Parameter available in simulation with m5 initparam")
# Checkpointing options
###Note that performing checkpointing via python script files will override
diff -r f1a69b7246f7 -r 78f27ef5e919 configs/example/fs.py
--- a/configs/example/fs.py Mon Jan 09 18:08:20 2012 -0600
+++ b/configs/example/fs.py Mon Jan 09 18:08:20 2012 -0600
@@ -151,6 +151,8 @@
if options.script is not None:
test_sys.readfile = options.script
+test_sys.init_param = options.init_param
+
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
CacheConfig.config_cache(options, test_sys)
@@ -199,6 +201,7 @@
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
+ drive_sys.init_param = options.init_param
root = makeDualRoot(test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
root = Root(system=test_sys)
diff -r f1a69b7246f7 -r 78f27ef5e919 src/arch/arm/isa/insts/m5ops.isa
--- a/src/arch/arm/isa/insts/m5ops.isa Mon Jan 09 18:08:20 2012 -0600
+++ b/src/arch/arm/isa/insts/m5ops.isa Mon Jan 09 18:08:20 2012 -0600
@@ -191,16 +191,18 @@
initparamCode = '''
#if FULL_SYSTEM
- Rt = PseudoInst::initParam(xc->tcBase());
+ uint64_t ip_val = PseudoInst::initParam(xc->tcBase());
+ R0 = bits(ip_val, 31, 0);
+ R1 = bits(ip_val, 63, 32);
#else
PseudoInst::panicFsOnlyPseudoInst("initparam");
- Rt = 0;
#endif
'''
initparamIop = InstObjParams("initparam", "Initparam", "PredOp",
{ "code": initparamCode,
- "predicate_test": predicateTest })
+ "predicate_test": predicateTest },
+ ["IsNonSpeculative"])
header_output += BasicDeclare.subst(initparamIop)
decoder_output += BasicConstructor.subst(initparamIop)
exec_output += PredOpExecute.subst(initparamIop)
diff -r f1a69b7246f7 -r 78f27ef5e919 util/m5/m5.c
--- a/util/m5/m5.c Mon Jan 09 18:08:20 2012 -0600
+++ b/util/m5/m5.c Mon Jan 09 18:08:20 2012 -0600
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2011 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2003-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -160,8 +172,8 @@
if (argc != 0)
usage();
-
- printf("%ld", m5_initparam());
+ uint64_t val = m5_initparam();
+ printf("%"PRIu64, val);
}
void
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