[gem5-dev] changeset in gem5: X86: Add memory fence to I/O instructions

[Nilay Vaish]

changeset 2c7ece076c8b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=2c7ece076c8b
description:
        X86: Add memory fence to I/O instructions

diffstat:

 src/arch/x86/isa/insts/general_purpose/input_output/general_io.py |  8 ++++++++
 src/arch/x86/isa/insts/general_purpose/input_output/string_io.py  |  8 ++++++++
 2 files changed, 16 insertions(+), 0 deletions(-)

diffs (97 lines):

diff -r 7945abdd05cb -r 2c7ece076c8b 
src/arch/x86/isa/insts/general_purpose/input_output/general_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Tue Jan 
10 06:35:40 2012 -0600
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/general_io.py Mon Jan 
09 20:13:31 2012 -0600
@@ -42,26 +42,34 @@
     def macroop IN_R_I {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=asz
+        mfence
         ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 
     def macroop IN_R_R {
         zexti t2, regm, 15, dataSize=8
+        mfence
         ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 
     def macroop OUT_I_R {
         .adjust_imm trimImm(8)
         limm t1, imm, dataSize=8
+        mfence
         st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 
     def macroop OUT_R_R {
         zexti t2, reg, 15, dataSize=8
+        mfence
         st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
             nonSpec=True
+        mfence
     };
 '''
diff -r 7945abdd05cb -r 2c7ece076c8b 
src/arch/x86/isa/insts/general_purpose/input_output/string_io.py
--- a/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py  Tue Jan 
10 06:35:40 2012 -0600
+++ b/src/arch/x86/isa/insts/general_purpose/input_output/string_io.py  Mon Jan 
09 20:13:31 2012 -0600
@@ -45,9 +45,11 @@
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
         nonSpec=True
     st t6, es, [1, t0, rdi]
+    mfence
 
     add rdi, rdi, t3, dataSize=asz
 };
@@ -63,6 +65,7 @@
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
 topOfLoop:
     ld t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
         nonSpec=True
@@ -72,6 +75,7 @@
     add rdi, rdi, t3, dataSize=asz
     br label("topOfLoop"), flags=(nCEZF,)
 end:
+    mfence
     fault "NoFault"
 };
 
@@ -84,9 +88,11 @@
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
     ld t6, ds, [1, t0, rsi]
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
         nonSpec=True
+    mfence
 
     add rsi, rsi, t3, dataSize=asz
 };
@@ -102,6 +108,7 @@
 
     zexti t2, reg, 15, dataSize=8
 
+    mfence
 topOfLoop:
     ld t6, ds, [1, t0, rsi]
     st t6, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
@@ -111,6 +118,7 @@
     add rsi, rsi, t3, dataSize=asz
     br label("topOfLoop"), flags=(nCEZF,)
 end:
+    mfence
     fault "NoFault"
 };
 '''
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev