Hi Andreas,
For the tip of the repository when you sent this message (508bbec99e58), this one passes for me. Ali On 11.01.2012 10:06, Andreas Hansson wrote: > Hi guys, > > With the changesets that were pushed yesterday one regression is failing (see below). I do not know which changeset caused the difference, but it seems to be scheduling related (given the small magnitude). Could the people that pushed figure out if it is reasonable and makes sense, and if so update the reference values? > > Andreas > > build/ARM_SE/tests/opt/long/20.parser/arm/linux/o3-timing FAILED! > > ===== Statistics differences ===== > Maximum error magnitude: +0.000436% > > Reference New Value Abs Diff Pct Chg > Key statistics: > > host_inst_rate 102660 111197 8537 +8.32% > host_mem_usage 223104 256704 33600 +15.06% > sim_insts 573341162 573341162 0 +0.00% > sim_ticks 274198757500 274198757500 0 +0.00% > > Differences > 0%: > > system.cpu.l2cache.occ_percent::0 0.229426 0.229425 -0.000001 -0.00% > system.cpu.l2cache.occ_percent::1 0.413308 0.413309 0.000001 +0.00% > system.cpu.l2cache.occ_blocks::0 7517.825600 7517.812526 -0.013074 -0.00% > system.cpu.l2cache.occ_blocks::1 13543.290586 13543.303660 0.013074 +0.00% > system.cpu.l2cache.ReadReq_mshr_miss_latency 4037687500 4037689500 2000 +0.00% > system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31050.297223 31050.312603 0.015380 +0.00% > system.cpu.l2cache.ReadReq_avg_miss_latency 34205.519161 34205.534539 0.015378 +0.00% > system.cpu.l2cache.ReadReq_miss_latency 4448633000 4448635000 2000 +0.00% > system.cpu.l2cache.demand_mshr_miss_latency 7393309500 7393311500 2000 +0.00% > system.cpu.l2cache.overall_mshr_miss_latency 7393309500 7393311500 2000 +0.00% > system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.036137 31030.044531 0.008394 +0.00% > system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.036137 31030.044531 0.008394 +0.00% > system.cpu.l2cache.demand_avg_miss_latency 34224.186048 34224.194442 0.008394 +0.00% > system.cpu.l2cache.overall_avg_miss_latency 34224.186048 34224.194442 0.008394 +0.00% > system.cpu.l2cache.demand_miss_latency 8155007500 8155009500 2000 +0.00% > system.cpu.l2cache.overall_miss_latency 8155007500 8155009500 2000 +0.00% > > -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
