changeset cd48e2802644 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=cd48e2802644
description:
MEM: Removing the default port peer from Python ports
In preparation for the introduction of Master and Slave ports, this
patch removes the default port parameter in the Python port and thus
forces the argument list of the Port to contain only the
description. The drawback at this point is that the config port and
dma port of PCI and DMA devices have to be connected explicitly. This
is key for future diversification as the pio and config port are
slaves, but the dma port is a master.
diffstat:
configs/common/FSConfig.py | 12 ++++++++++++
src/dev/Device.py | 2 +-
src/dev/Pci.py | 2 +-
src/dev/arm/RealView.py | 11 +++++++++++
src/dev/pcidev.cc | 4 ++--
src/dev/x86/SouthBridge.py | 2 ++
src/python/m5/SimObject.py | 2 --
src/python/m5/params.py | 5 +----
8 files changed, 30 insertions(+), 10 deletions(-)
diffs (164 lines):
diff -r 2f1a3e335255 -r cd48e2802644 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Tue Jan 17 12:55:09 2012 -0600
+++ b/configs/common/FSConfig.py Tue Jan 17 12:55:09 2012 -0600
@@ -84,7 +84,11 @@
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.iobus)
self.tsunami.ide.pio = self.iobus.port
+ self.tsunami.ide.config = self.iobus.port
+ self.tsunami.ide.dma = self.iobus.port
self.tsunami.ethernet.pio = self.iobus.port
+ self.tsunami.ethernet.config = self.iobus.port
+ self.tsunami.ethernet.dma = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
@@ -129,7 +133,11 @@
self.tsunami = BaseTsunami()
self.tsunami.attachIO(self.piobus)
self.tsunami.ide.pio = self.piobus.port
+ self.tsunami.ide.config = self.piobus.port
+ self.tsunami.ide.dma = self.piobus.port
self.tsunami.ethernet.pio = self.piobus.port
+ self.tsunami.ethernet.config = self.piobus.port
+ self.tsunami.ethernet.dma = self.piobus.port
#
# Store the dma devices for later connection to dma ruby ports.
@@ -324,7 +332,11 @@
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.port
+ self.malta.ide.config = self.iobus.port
+ self.malta.ide.dma = self.iobus.port
self.malta.ethernet.pio = self.iobus.port
+ self.malta.ethernet.config = self.iobus.port
+ self.malta.ethernet.dma = self.iobus.port
self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
read_only = True))
self.intrctrl = IntrControl()
diff -r 2f1a3e335255 -r cd48e2802644 src/dev/Device.py
--- a/src/dev/Device.py Tue Jan 17 12:55:09 2012 -0600
+++ b/src/dev/Device.py Tue Jan 17 12:55:09 2012 -0600
@@ -46,7 +46,7 @@
class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
- dma = Port(Self.pio.peerObj.port, "DMA port")
+ dma = Port("DMA port")
min_backoff_delay = Param.Latency('4ns',
"min time between a nack packet being received and the next request made
by the device")
max_backoff_delay = Param.Latency('10us',
diff -r 2f1a3e335255 -r cd48e2802644 src/dev/Pci.py
--- a/src/dev/Pci.py Tue Jan 17 12:55:09 2012 -0600
+++ b/src/dev/Pci.py Tue Jan 17 12:55:09 2012 -0600
@@ -41,7 +41,7 @@
class PciDevice(DmaDevice):
type = 'PciDevice'
abstract = True
- config = Port(Self.pio.peerObj.port, "PCI configuration space port")
+ config = Port("PCI configuration space port")
pci_bus = Param.Int("PCI bus")
pci_dev = Param.Int("PCI device number")
pci_func = Param.Int("PCI function code")
diff -r 2f1a3e335255 -r cd48e2802644 src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py Tue Jan 17 12:55:09 2012 -0600
+++ b/src/dev/arm/RealView.py Tue Jan 17 12:55:09 2012 -0600
@@ -199,9 +199,12 @@
self.timer0.pio = bus.port
self.timer1.pio = bus.port
self.clcd.pio = bus.port
+ self.clcd.dma = bus.port
self.kmi0.pio = bus.port
self.kmi1.pio = bus.port
self.cf_ctrl.pio = bus.port
+ self.cf_ctrl.config = bus.port
+ self.cf_ctrl.dma = bus.port
self.dmac_fake.pio = bus.port
self.uart1_fake.pio = bus.port
self.uart2_fake.pio = bus.port
@@ -274,6 +277,7 @@
self.timer0.pio = bus.port
self.timer1.pio = bus.port
self.clcd.pio = bus.port
+ self.clcd.dma = bus.port
self.kmi0.pio = bus.port
self.kmi1.pio = bus.port
self.dmac_fake.pio = bus.port
@@ -364,13 +368,20 @@
self.elba_timer0.pio = bus.port
self.elba_timer1.pio = bus.port
self.clcd.pio = bus.port
+ self.clcd.dma = bus.port
self.kmi0.pio = bus.port
self.kmi1.pio = bus.port
self.elba_kmi0.pio = bus.port
self.elba_kmi1.pio = bus.port
self.cf_ctrl.pio = bus.port
+ self.cf_ctrl.config = bus.port
+ self.cf_ctrl.dma = bus.port
self.ide.pio = bus.port
+ self.ide.config = bus.port
+ self.ide.dma = bus.port
self.ethernet.pio = bus.port
+ self.ethernet.config = bus.port
+ self.ethernet.dma = bus.port
self.pciconfig.pio = bus.default
bus.use_default_range = True
diff -r 2f1a3e335255 -r cd48e2802644 src/dev/pcidev.cc
--- a/src/dev/pcidev.cc Tue Jan 17 12:55:09 2012 -0600
+++ b/src/dev/pcidev.cc Tue Jan 17 12:55:09 2012 -0600
@@ -150,8 +150,8 @@
void
PciDev::init()
{
- if (!configPort)
- panic("pci config port not connected to anything!");
+ if (!configPort && !configPort->isConnected())
+ panic("PCI config port on %s not connected to anything!\n", name());
configPort->sendRangeChange();
PioDevice::init();
}
diff -r 2f1a3e335255 -r cd48e2802644 src/dev/x86/SouthBridge.py
--- a/src/dev/x86/SouthBridge.py Tue Jan 17 12:55:09 2012 -0600
+++ b/src/dev/x86/SouthBridge.py Tue Jan 17 12:55:09 2012 -0600
@@ -105,6 +105,8 @@
self.cmos.pio = bus.port
self.dma1.pio = bus.port
self.ide.pio = bus.port
+ self.ide.config = bus.port
+ self.ide.dma = bus.port
self.keyboard.pio = bus.port
self.pic1.pio = bus.port
self.pic2.pio = bus.port
diff -r 2f1a3e335255 -r cd48e2802644 src/python/m5/SimObject.py
--- a/src/python/m5/SimObject.py Tue Jan 17 12:55:09 2012 -0600
+++ b/src/python/m5/SimObject.py Tue Jan 17 12:55:09 2012 -0600
@@ -273,8 +273,6 @@
assert(not hasattr(port, 'name'))
port.name = name
cls._ports[name] = port
- if hasattr(port, 'default'):
- cls._cls_get_port_ref(name).connect(port.default)
# same as _get_port_ref, effectively, but for classes
def _cls_get_port_ref(cls, attr):
diff -r 2f1a3e335255 -r cd48e2802644 src/python/m5/params.py
--- a/src/python/m5/params.py Tue Jan 17 12:55:09 2012 -0600
+++ b/src/python/m5/params.py Tue Jan 17 12:55:09 2012 -0600
@@ -1488,13 +1488,10 @@
# logical port in the SimObject class, not a particular port on a
# SimObject instance. The latter are represented by PortRef objects.
class Port(object):
- # Port("description") or Port(default, "description")
+ # Port("description")
def __init__(self, *args):
if len(args) == 1:
self.desc = args[0]
- elif len(args) == 2:
- self.default = args[0]
- self.desc = args[1]
else:
raise TypeError, 'wrong number of arguments'
# self.name is set by SimObject class on assignment
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