----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.m5sim.org/r/1005/ -----------------------------------------------------------
Review request for Default. Summary ------- MEM: Make the RubyPort physMemPort a PioPort instead of M5Port This patch makes the physMemPort of the RubyPort a PioPort rather than an M5Port. This reflects the fact that the M5Port and PioPort have different roles. The M5Port is really a coherent slave that is connected to the CPUs and other coherent masters of the system, e.g. DMA ports. The PioPort, on the other hand, is a master port that is connected to the memory and other slaves, for example the pio devices. This simplifies future changes into master/slave ports and is consistent with the port roles throughout the system. Diffs ----- src/mem/ruby/system/RubyPort.hh 03e09db82c80 src/mem/ruby/system/RubyPort.cc 03e09db82c80 Diff: http://reviews.m5sim.org/r/1005/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas _______________________________________________ gem5-dev mailing list gem5-dev@gem5.org http://m5sim.org/mailman/listinfo/gem5-dev
