changeset 7b4d80b26e35 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7b4d80b26e35
description:
configs: A more realistic configuration of an ARM-like processor
diffstat:
configs/common/CacheConfig.py | 29 +++++++++++++++++++++++------
configs/common/Options.py | 3 ++-
configs/common/Simulation.py | 8 ++++++--
3 files changed, 31 insertions(+), 9 deletions(-)
diffs (90 lines):
diff -r bbcc7afd82cb -r 7b4d80b26e35 configs/common/CacheConfig.py
--- a/configs/common/CacheConfig.py Wed Jan 25 12:44:43 2012 -0500
+++ b/configs/common/CacheConfig.py Thu Jan 26 14:53:48 2012 -0500
@@ -32,11 +32,17 @@
import m5
from m5.objects import *
from Caches import *
+from O3_ARM_v7a import *
def config_cache(options, system):
if options.l2cache:
- system.l2 = L2Cache(size = options.l2_size, assoc = options.l2_assoc,
- block_size=options.cacheline_size)
+ if options.cpu_type == "arm_detailed":
+ system.l2 = O3_ARM_v7aL2(size = options.l2_size, assoc =
options.l2_assoc,
+ block_size=options.cacheline_size)
+ else:
+ system.l2 = L2Cache(size = options.l2_size, assoc =
options.l2_assoc,
+ block_size=options.cacheline_size)
+
system.tol2bus = Bus()
system.l2.cpu_side = system.tol2bus.port
system.l2.mem_side = system.membus.port
@@ -44,10 +50,21 @@
for i in xrange(options.num_cpus):
if options.caches:
- icache = L1Cache(size = options.l1i_size, assoc =
options.l1i_assoc,
- block_size=options.cacheline_size)
- dcache = L1Cache(size = options.l1d_size, assoc =
options.l1d_assoc,
- block_size=options.cacheline_size)
+ if options.cpu_type == "arm_detailed":
+ icache = O3_ARM_v7a_ICache(size = options.l1i_size,
+ assoc = options.l1i_assoc,
+ block_size=options.cacheline_size)
+ dcache = O3_ARM_v7a_DCache(size = options.l1d_size,
+ assoc = options.l1d_assoc,
+ block_size=options.cacheline_size)
+ else:
+ icache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc,
+ block_size=options.cacheline_size)
+ dcache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc,
+ block_size=options.cacheline_size)
+
if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
PageTableWalkerCache(),
diff -r bbcc7afd82cb -r 7b4d80b26e35 configs/common/Options.py
--- a/configs/common/Options.py Wed Jan 25 12:44:43 2012 -0500
+++ b/configs/common/Options.py Thu Jan 26 14:53:48 2012 -0500
@@ -28,7 +28,8 @@
# system options
parser.add_option("--cpu-type", type="choice", default="atomic",
- choices = ["atomic", "timing", "detailed", "inorder"],
+ choices = ["atomic", "timing", "detailed", "inorder",
+ "arm_detailed"],
help = "type of cpu to run with")
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
diff -r bbcc7afd82cb -r 7b4d80b26e35 configs/common/Simulation.py
--- a/configs/common/Simulation.py Wed Jan 25 12:44:43 2012 -0500
+++ b/configs/common/Simulation.py Thu Jan 26 14:53:48 2012 -0500
@@ -34,6 +34,7 @@
from m5.defines import buildEnv
from m5.objects import *
from m5.util import *
+from O3_ARM_v7a import *
addToPath('../common')
@@ -42,11 +43,14 @@
atomic = False
if options.cpu_type == "timing":
class TmpClass(TimingSimpleCPU): pass
- elif options.cpu_type == "detailed":
+ elif options.cpu_type == "detailed" or options.cpu_type == "arm_detailed":
if not options.caches and not options.ruby:
print "O3 CPU must be used with caches"
sys.exit(1)
- class TmpClass(DerivO3CPU): pass
+ if options.cpu_type == "arm_detailed":
+ class TmpClass(O3_ARM_v7a_3): pass
+ else:
+ class TmpClass(DerivO3CPU): pass
elif options.cpu_type == "inorder":
if not options.caches:
print "InOrder CPU must be used with caches"
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