[gem5-dev] changeset in gem5: O3 CPU LSQ: Implement TSO

[Nilay Vaish]

changeset b3995530319f in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=b3995530319f
description:
        O3 CPU LSQ: Implement TSO
        This patch makes O3's LSQ maintain total order between stores. 
Essentially
        only the store at the head of the store buffer is allowed to be in 
flight.
        Only after that store completes, the next store is issued to the memory
        system. By default, the x86 architecture will have TSO.

diffstat:

 src/cpu/o3/O3CPU.py         |   2 ++
 src/cpu/o3/lsq_unit.hh      |   6 ++++++
 src/cpu/o3/lsq_unit_impl.hh |  12 +++++++++++-
 3 files changed, 19 insertions(+), 1 deletions(-)

diffs (82 lines):

diff -r 7ee2e35da276 -r b3995530319f src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py       Fri Jan 27 12:54:11 2012 -0500
+++ b/src/cpu/o3/O3CPU.py       Sat Jan 28 19:09:04 2012 -0600
@@ -143,3 +143,5 @@
     smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
     smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
 
+    needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
+                          "Enable TSO Memory model")
diff -r 7ee2e35da276 -r b3995530319f src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh    Fri Jan 27 12:54:11 2012 -0500
+++ b/src/cpu/o3/lsq_unit.hh    Sat Jan 28 19:09:04 2012 -0600
@@ -453,6 +453,9 @@
     /** Has the blocked load been handled. */
     bool loadBlockedHandled;
 
+    /** Whether or not a store is in flight. */
+    bool storeInFlight;
+
     /** The sequence number of the blocked load. */
     InstSeqNum blockedLoadSeqNum;
 
@@ -466,6 +469,9 @@
     /** The packet that is pending free cache ports. */
     PacketPtr pendingPkt;
 
+    /** Flag for memory model. */
+    bool needsTSO;
+
     // Will also need how many read/write ports the Dcache has.  Or keep track
     // of that in stage that is one level up, and only call executeLoad/Store
     // the appropriate number of times.
diff -r 7ee2e35da276 -r b3995530319f src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh       Fri Jan 27 12:54:11 2012 -0500
+++ b/src/cpu/o3/lsq_unit_impl.hh       Sat Jan 28 19:09:04 2012 -0600
@@ -138,7 +138,7 @@
 LSQUnit<Impl>::LSQUnit()
     : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false),
       isStoreBlocked(false), isLoadBlocked(false),
-      loadBlockedHandled(false), hasPendingPkt(false)
+      loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false)
 {
 }
 
@@ -182,6 +182,7 @@
     memDepViolator = NULL;
 
     blockedLoadSeqNum = 0;
+    needsTSO = params->needsTSO;
 }
 
 template<class Impl>
@@ -770,6 +771,7 @@
            storeWBIdx != storeTail &&
            storeQueue[storeWBIdx].inst &&
            storeQueue[storeWBIdx].canWB &&
+           ((!needsTSO) || (!storeInFlight)) &&
            usedPorts < cachePorts) {
 
         if (isStoreBlocked || lsq->cacheBlocked()) {
@@ -1090,6 +1092,10 @@
 #endif
     }
 
+    if (needsTSO) {
+        storeInFlight = true;
+    }
+
     incrStIdx(storeWBIdx);
 }
 
@@ -1163,6 +1169,10 @@
 
     storeQueue[store_idx].inst->setCompleted();
 
+    if (needsTSO) {
+        storeInFlight = false;
+    }
+
     // Tell the checker we've completed this instruction.  Some stores
     // may get reported twice to the checker, but the checker can
     // handle that case.
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