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Ship it! Ship It! - Andreas Hansson On Jan. 29, 2012, 10:21 p.m., Koan-Sin Tan wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/986/ > ----------------------------------------------------------- > > (Updated Jan. 29, 2012, 10:21 p.m.) > > > Review request for Default. > > > Description > ------- > > clang: Enable compiling gem5 using clang 2.9 and 3.0 > > This patch adds the necessary flags to the SConstruct and SConscript > files for compiling using clang 2.9 and later (on Ubuntu et al and OSX > XCode 4.2), and also cleans up a bunch of compiler warnings found by > clang. Most of the warnings are related to hidden virtual functions, > comparisons with unsigneds >= 0, and if-statements with empty > bodies. A number of mismatches between struct and class are also > fixed. clang 2.8 is not working as it has problems with class names > that occur in multiple namespaces (e.g. Statistics in > kernel_stats.hh). > > clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which > causes confusion between the container std::set and the function > Packet::set, and this is currently addressed by not including the > entire namespace std, but rather selecting e.g. "using std::vector" in > the appropriate places. > > > Diffs > ----- > > SConstruct UNKNOWN > ext/libelf/SConscript UNKNOWN > src/SConscript UNKNOWN > src/arch/alpha/tlb.hh UNKNOWN > src/arch/alpha/tlb.cc UNKNOWN > src/arch/arm/insts/static_inst.hh UNKNOWN > src/arch/arm/insts/vfp.hh UNKNOWN > src/arch/arm/isa/templates/basic.isa UNKNOWN > src/arch/arm/miscregs.cc UNKNOWN > src/arch/generic/memhelpers.hh UNKNOWN > src/arch/mips/faults.hh UNKNOWN > src/arch/mips/faults.cc UNKNOWN > src/arch/x86/bios/acpi.hh UNKNOWN > src/arch/x86/bios/intelmp.hh UNKNOWN > src/arch/x86/bios/intelmp.cc UNKNOWN > src/arch/x86/bios/smbios.hh UNKNOWN > src/base/fast_alloc.cc UNKNOWN > src/base/range_map.hh UNKNOWN > src/base/remote_gdb.hh UNKNOWN > src/base/stl_helpers.hh UNKNOWN > src/cpu/base.hh UNKNOWN > src/cpu/base.cc UNKNOWN > src/cpu/func_unit.hh UNKNOWN > src/cpu/inorder/cpu.hh UNKNOWN > src/cpu/inorder/cpu.cc UNKNOWN > src/cpu/inorder/resource.hh UNKNOWN > src/cpu/inorder/resource.cc UNKNOWN > src/cpu/inorder/resource_pool.hh UNKNOWN > src/cpu/inorder/resource_pool.cc UNKNOWN > src/cpu/inorder/resources/cache_unit.hh UNKNOWN > src/cpu/inorder/thread_context.cc UNKNOWN > src/cpu/nativetrace.hh UNKNOWN > src/cpu/o3/bpred_unit.hh UNKNOWN > src/cpu/o3/commit.hh UNKNOWN > src/cpu/o3/cpu.hh UNKNOWN > src/cpu/o3/cpu.cc UNKNOWN > src/cpu/o3/decode.hh UNKNOWN > src/cpu/o3/decode_impl.hh UNKNOWN > src/cpu/o3/fetch.hh UNKNOWN > src/cpu/o3/fu_pool.hh UNKNOWN > src/cpu/o3/fu_pool.cc UNKNOWN > src/cpu/o3/iew.hh UNKNOWN > src/cpu/o3/iew_impl.hh UNKNOWN > src/cpu/o3/inst_queue.hh UNKNOWN > src/cpu/o3/inst_queue_impl.hh UNKNOWN > src/cpu/o3/lsq.hh UNKNOWN > src/cpu/o3/lsq_unit.hh UNKNOWN > src/cpu/o3/mem_dep_unit.hh UNKNOWN > src/cpu/o3/mem_dep_unit.cc UNKNOWN > src/cpu/o3/rename.hh UNKNOWN > src/cpu/o3/sat_counter.hh UNKNOWN > src/cpu/quiesce_event.hh UNKNOWN > src/cpu/simple/atomic.hh UNKNOWN > src/cpu/simple/atomic.cc UNKNOWN > src/cpu/simple/base.hh UNKNOWN > src/cpu/simple/base.cc UNKNOWN > src/cpu/simple/timing.hh UNKNOWN > src/cpu/simple/timing.cc UNKNOWN > src/cpu/static_inst.hh UNKNOWN > src/dev/alpha/tsunami_cchip.cc UNKNOWN > src/dev/alpha/tsunami_io.cc UNKNOWN > src/dev/arm/pl111.hh UNKNOWN > src/dev/arm/pl111.cc UNKNOWN > src/dev/copy_engine.cc UNKNOWN > src/dev/disk_image.hh UNKNOWN > src/dev/disk_image.cc UNKNOWN > src/dev/ide_ctrl.cc UNKNOWN > src/dev/ns_gige.cc UNKNOWN > src/dev/pciconfigall.cc UNKNOWN > src/dev/pcidev.cc UNKNOWN > src/mem/cache/base.hh UNKNOWN > src/mem/cache/base.cc UNKNOWN > src/mem/cache/tags/iic.cc UNKNOWN > src/mem/cache/tags/iic_repl/gen.hh UNKNOWN > src/mem/cache/tags/iic_repl/gen.cc UNKNOWN > src/mem/cache/tags/iic_repl/repl.hh UNKNOWN > src/mem/packet.hh UNKNOWN > src/mem/ruby/system/Sequencer.hh UNKNOWN > src/python/m5/SimObject.py UNKNOWN > src/sim/core.hh UNKNOWN > src/sim/process.hh UNKNOWN > src/sim/process.cc UNKNOWN > src/sim/process_impl.hh UNKNOWN > src/sim/serialize.cc UNKNOWN > src/sim/sim_object.hh UNKNOWN > src/sim/sim_object.cc UNKNOWN > src/sim/syscall_emul.hh UNKNOWN > > Diff: http://reviews.gem5.org/r/986/diff/diff > > > Testing > ------- > > > Thanks, > > Koan-Sin Tan > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
