changeset bb0aaf3ffa18 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=bb0aaf3ffa18
description:
MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
This patch makes the physMemPort of the RubyPort a PioPort rather than
an M5Port. This reflects the fact that the M5Port and PioPort have
different roles. The M5Port is really a coherent slave that is
connected to the CPUs and other coherent masters of the system,
e.g. DMA ports. The PioPort, on the other hand, is a master port that
is connected to the memory and other slaves, for example the pio
devices.
This simplifies future changes into master/slave ports and is
consistent with the port roles throughout the system.
diffstat:
src/mem/ruby/system/RubyPort.cc | 3 +--
src/mem/ruby/system/RubyPort.hh | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diffs (25 lines):
diff -r 0a742249f76b -r bb0aaf3ffa18 src/mem/ruby/system/RubyPort.cc
--- a/src/mem/ruby/system/RubyPort.cc Mon Jan 30 03:44:25 2012 -0500
+++ b/src/mem/ruby/system/RubyPort.cc Mon Jan 30 05:38:24 2012 -0500
@@ -88,8 +88,7 @@
// RubyPort should only have one port to physical memory
assert (physMemPort == NULL);
- physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
- ruby_system, access_phys_mem);
+ physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
return physMemPort;
}
diff -r 0a742249f76b -r bb0aaf3ffa18 src/mem/ruby/system/RubyPort.hh
--- a/src/mem/ruby/system/RubyPort.hh Mon Jan 30 03:44:25 2012 -0500
+++ b/src/mem/ruby/system/RubyPort.hh Mon Jan 30 05:38:24 2012 -0500
@@ -155,7 +155,7 @@
uint16_t m_port_id;
uint64_t m_request_cnt;
- M5Port* physMemPort;
+ PioPort* physMemPort;
/*! Vector of CPU Port attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;
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