changeset 64a7bf8fa56c in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=64a7bf8fa56c
description:
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
diffstat:
src/arch/arm/isa.cc | 53 +++-
src/arch/arm/isa/insts/m5ops.isa | 4 +-
src/arch/arm/isa/insts/misc.isa | 8 +-
src/arch/arm/table_walker.cc | 25 +-
src/arch/arm/table_walker.hh | 5 +-
src/arch/arm/tlb.cc | 21 +-
src/arch/arm/tlb.hh | 9 +-
src/arch/arm/utility.cc | 5 +
src/cpu/BaseCPU.py | 6 +-
src/cpu/CheckerCPU.py | 2 +-
src/cpu/DummyChecker.py | 42 ++
src/cpu/SConscript | 2 +
src/cpu/base.cc | 39 ++-
src/cpu/base_dyn_inst.hh | 84 ++++-
src/cpu/base_dyn_inst_impl.hh | 11 +-
src/cpu/checker/cpu.cc | 375 ++++++++++++++------------
src/cpu/checker/cpu.hh | 123 ++++++-
src/cpu/checker/cpu_impl.hh | 535 +++++++++++++++++++++++++------------
src/cpu/checker/thread_context.hh | 108 +++++-
src/cpu/dummy_checker_builder.cc | 100 +++++++
src/cpu/o3/O3CPU.py | 16 +-
src/cpu/o3/O3Checker.py | 2 +-
src/cpu/o3/checker_builder.cc | 31 +-
src/cpu/o3/commit_impl.hh | 12 +-
src/cpu/o3/cpu.cc | 3 +-
src/cpu/o3/cpu.hh | 2 +-
src/cpu/o3/dyn_inst_impl.hh | 8 +-
src/cpu/o3/fetch_impl.hh | 8 +-
src/cpu/o3/iew_impl.hh | 14 +-
src/cpu/o3/lsq_unit_impl.hh | 14 +-
src/cpu/o3/thread_context.hh | 21 +
src/cpu/o3/thread_context_impl.hh | 17 +-
src/cpu/simple/BaseSimpleCPU.py | 9 +
src/cpu/simple/base.cc | 23 +-
src/cpu/simple/base.hh | 21 +
src/cpu/simple_thread.hh | 30 ++-
src/cpu/thread_context.hh | 29 ++
src/mem/bus.cc | 3 +-
38 files changed, 1346 insertions(+), 474 deletions(-)
diffs (truncated from 3282 to 300 lines):
diff -r fd510b6e124d -r 64a7bf8fa56c src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Mon Jan 30 09:37:06 2012 -0500
+++ b/src/arch/arm/isa.cc Tue Jan 31 07:46:03 2012 -0800
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2011 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -39,12 +39,17 @@
*/
#include "arch/arm/isa.hh"
+#include "config/use_checker.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
+#if USE_CHECKER
+#include "cpu/checker/cpu.hh"
+#endif
+
namespace ArmISA
{
@@ -279,7 +284,11 @@
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
+#if USE_CHECKER
+ tc->pcStateNoRecord(pc);
+#else
tc->pcState(pc);
+#endif //USE_CHECKER
} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
misc_reg < MISCREG_CP15_END) {
panic("Unimplemented CP15 register %s wrote with %#x.\n",
@@ -382,6 +391,14 @@
oc = sys->getThreadContext(x);
oc->getDTBPtr()->allCpusCaching();
oc->getITBPtr()->allCpusCaching();
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getDTBPtr()->allCpusCaching();
+ checker->getITBPtr()->allCpusCaching();
+ }
+#endif
}
return;
}
@@ -399,6 +416,14 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAll();
oc->getDTBPtr()->flushAll();
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushAll();
+ checker->getDTBPtr()->flushAll();
+ }
+#endif
}
return;
case MISCREG_ITLBIALL:
@@ -417,6 +442,16 @@
bits(newVal, 7,0));
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
+ bits(newVal, 7,0));
+ }
+#endif
}
return;
case MISCREG_TLBIASIDIS:
@@ -427,6 +462,14 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
+ checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
+ }
+#endif
}
return;
case MISCREG_TLBIMVAAIS:
@@ -437,6 +480,14 @@
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+#if USE_CHECKER
+ CheckerCPU *checker =
+ dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ if (checker) {
+ checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
+ checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
+ }
+#endif
}
return;
case MISCREG_ITLBIMVA:
diff -r fd510b6e124d -r 64a7bf8fa56c src/arch/arm/isa/insts/m5ops.isa
--- a/src/arch/arm/isa/insts/m5ops.isa Mon Jan 30 09:37:06 2012 -0500
+++ b/src/arch/arm/isa/insts/m5ops.isa Tue Jan 31 07:46:03 2012 -0800
@@ -247,7 +247,7 @@
m5checkpointIop = InstObjParams("m5checkpoint", "M5checkpoint", "PredOp",
{ "code": m5checkpoint_code,
"predicate_test": predicateTest },
- ["IsNonSpeculative"])
+ ["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(m5checkpointIop)
decoder_output += BasicConstructor.subst(m5checkpointIop)
exec_output += PredOpExecute.subst(m5checkpointIop)
@@ -260,7 +260,7 @@
m5readfileIop = InstObjParams("m5readfile", "M5readfile", "PredOp",
{ "code": m5readfileCode,
"predicate_test": predicateTest },
- ["IsNonSpeculative"])
+ ["IsNonSpeculative", "IsUnverifiable"])
header_output += BasicDeclare.subst(m5readfileIop)
decoder_output += BasicConstructor.subst(m5readfileIop)
exec_output += PredOpExecute.subst(m5readfileIop)
diff -r fd510b6e124d -r 64a7bf8fa56c src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Mon Jan 30 09:37:06 2012 -0500
+++ b/src/arch/arm/isa/insts/misc.isa Tue Jan 31 07:46:03 2012 -0800
@@ -525,7 +525,8 @@
{ "code" : wfeCode,
"pred_fixup" : wfePredFixUpCode,
"predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+ ["IsNonSpeculative", "IsQuiesce",
+ "IsSerializeAfter", "IsUnverifiable"])
header_output += BasicDeclare.subst(wfeIop)
decoder_output += BasicConstructor.subst(wfeIop)
exec_output += QuiescePredOpExecuteWithFixup.subst(wfeIop)
@@ -542,7 +543,8 @@
'''
wfiIop = InstObjParams("wfi", "WfiInst", "PredOp", \
{ "code" : wfiCode, "predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsQuiesce", "IsSerializeAfter"])
+ ["IsNonSpeculative", "IsQuiesce",
+ "IsSerializeAfter", "IsUnverifiable"])
header_output += BasicDeclare.subst(wfiIop)
decoder_output += BasicConstructor.subst(wfiIop)
exec_output += QuiescePredOpExecute.subst(wfiIop)
@@ -565,7 +567,7 @@
'''
sevIop = InstObjParams("sev", "SevInst", "PredOp", \
{ "code" : sevCode, "predicate_test" : predicateTest },
- ["IsNonSpeculative", "IsSquashAfter"])
+ ["IsNonSpeculative", "IsSquashAfter", "IsUnverifiable"])
header_output += BasicDeclare.subst(sevIop)
decoder_output += BasicConstructor.subst(sevIop)
exec_output += PredOpExecute.subst(sevIop)
diff -r fd510b6e124d -r 64a7bf8fa56c src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Mon Jan 30 09:37:06 2012 -0500
+++ b/src/arch/arm/table_walker.cc Tue Jan 31 07:46:03 2012 -0800
@@ -107,8 +107,9 @@
Fault
TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode
_mode,
- TLB::Translation *_trans, bool _timing)
+ TLB::Translation *_trans, bool _timing, bool _functional)
{
+ assert(!(_functional && _timing));
if (!currState) {
// For atomic mode, a new WalkerState instance should be only created
// once per TLB. For timing mode, a new instance is generated for every
@@ -136,6 +137,7 @@
currState->fault = NoFault;
currState->contextId = _cid;
currState->timing = _timing;
+ currState->functional = _functional;
currState->mode = _mode;
/** @todo These should be cached or grabbed from cached copies in
@@ -230,12 +232,21 @@
stateQueueL1.size());
stateQueueL1.push_back(currState);
currState = NULL;
- } else {
+ } else if (!currState->functional) {
port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
NULL, (uint8_t*)&currState->l1Desc.data,
currState->tc->getCpuPtr()->ticks(1), flag);
doL1Descriptor();
f = currState->fault;
+ } else {
+ RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
+ port->sendFunctional(pkt);
+ doL1Descriptor();
+ delete req;
+ delete pkt;
+ f = currState->fault;
}
return f;
@@ -566,11 +577,19 @@
port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
&doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
currState->tc->getCpuPtr()->ticks(1));
- } else {
+ } else if (!currState->functional) {
port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
NULL, (uint8_t*)&currState->l2Desc.data,
currState->tc->getCpuPtr()->ticks(1));
doL2Descriptor();
+ } else {
+ RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0);
+ PacketPtr pkt = new Packet(req, MemCmd::ReadReq,
Packet::Broadcast);
+ pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
+ port->sendFunctional(pkt);
+ doL2Descriptor();
+ delete req;
+ delete pkt;
}
return;
default:
diff -r fd510b6e124d -r 64a7bf8fa56c src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Mon Jan 30 09:37:06 2012 -0500
+++ b/src/arch/arm/table_walker.hh Tue Jan 31 07:46:03 2012 -0800
@@ -294,6 +294,9 @@
/** If the mode is timing or atomic */
bool timing;
+ /** If the atomic mode should be functional */
+ bool functional;
+
/** Save mode for use in delayed response */
BaseTLB::Mode mode;
@@ -354,7 +357,7 @@
virtual Port *getPort(const std::string &if_name, int idx = -1);
Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
- TLB::Translation *_trans, bool timing);
+ TLB::Translation *_trans, bool timing, bool functional = false);
void setTlb(TLB *_tlb) { tlb = _tlb; }
void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
diff -r fd510b6e124d -r 64a7bf8fa56c src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Mon Jan 30 09:37:06 2012 -0500
+++ b/src/arch/arm/tlb.cc Tue Jan 31 07:46:03 2012 -0800
@@ -453,8 +453,11 @@
Fault
TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
- Translation *translation, bool &delay, bool timing)
+ Translation *translation, bool &delay, bool timing, bool functional)
{
+ // No such thing as a functional timing access
+ assert(!(timing && functional));
+
if (!miscRegValid) {
updateMiscReg(tc);
DPRINTF(TLBVerbose, "TLB variables changed!\n");
@@ -541,7 +544,7 @@
DPRINTF(TLB, "TLB Miss: Starting hardware table walker for %#x(%d)\n",
vaddr, contextId);
fault = tableWalker->walk(req, tc, contextId, mode, translation,
- timing);
+ timing, functional);
if (timing && fault == NoFault) {
delay = true;
// for timing mode, return and wait for table walk
@@ -701,6 +704,20 @@
}
Fault
+TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode)
+{
+ bool delay = false;
+ Fault fault;
+#if FULL_SYSTEM
+ fault = translateFs(req, tc, mode, NULL, delay, false, true);
+#else
+ fault = translateSe(req, tc, mode, NULL, delay, false);
+#endif
+ assert(!delay);
+ return fault;
+}
+
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