changeset 66bf413b0d5b in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=66bf413b0d5b
description:
SE/FS: Use the new FullSystem constant where possible.
diffstat:
src/arch/alpha/isa/decoder.isa | 10 +++++-----
src/arch/alpha/isa/fp.isa | 2 +-
src/arch/alpha/isa/main.isa | 2 ++
src/arch/alpha/tlb.cc | 3 ++-
src/arch/mips/faults.cc | 4 ++--
src/arch/mips/faults.hh | 7 ++++---
src/arch/mips/isa/decoder.isa | 10 +++++-----
src/arch/mips/isa/formats/control.isa | 8 ++++----
src/arch/mips/isa/formats/dsp.isa | 4 ++--
src/arch/mips/isa/formats/fp.isa | 4 ++--
src/arch/mips/isa/formats/unimp.isa | 6 +++---
src/arch/mips/isa/includes.isa | 2 ++
src/arch/sparc/isa/base.isa | 2 +-
src/arch/sparc/isa/includes.isa | 1 +
src/arch/x86/isa/decoder/one_byte_opcodes.isa | 2 +-
src/arch/x86/isa/decoder/two_byte_opcodes.isa | 4 ++--
src/arch/x86/isa/includes.isa | 1 +
17 files changed, 40 insertions(+), 32 deletions(-)
diffs (truncated from 395 to 300 lines):
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/alpha/isa/decoder.isa
--- a/src/arch/alpha/isa/decoder.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/alpha/isa/decoder.isa Fri Sep 30 00:27:16 2011 -0700
@@ -202,8 +202,8 @@
0x6c: decode RA {
31: decode IMM {
1: decode INTIMM {
- // return EV5 for FULL_SYSTEM and EV6 otherwise
- 1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }});
+ // return EV5 for FullSystem and EV6 otherwise
+ 1: implver({{ Rc = FullSystem ? 1 : 2 }});
}
}
}
@@ -780,7 +780,7 @@
* the parser to understand that.
*/
uint64_t unused_var M5_VAR_USED = Rb;
- Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick();
+ Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
}}, IsUnverifiable);
// All of the barrier instructions below do nothing in
@@ -805,14 +805,14 @@
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
}
- 0xe000: decode FULL_SYSTEM {
+ 0xe000: decode FullSystem {
0: FailUnimpl::rc_se();
default: BasicOperate::rc({{
Ra = IntrFlag;
IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable);
}
- 0xf000: decode FULL_SYSTEM {
+ 0xf000: decode FullSystem {
0: FailUnimpl::rs_se();
default: BasicOperate::rs({{
Ra = IntrFlag;
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/alpha/isa/fp.isa
--- a/src/arch/alpha/isa/fp.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/alpha/isa/fp.isa Fri Sep 30 00:27:16 2011 -0700
@@ -45,7 +45,7 @@
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{
Fault fault = NoFault; // dummy... this ipr access should not fault
- if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
+ if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault;
}
return fault;
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/alpha/isa/main.isa
--- a/src/arch/alpha/isa/main.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/alpha/isa/main.isa Fri Sep 30 00:27:16 2011 -0700
@@ -64,6 +64,7 @@
#include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh"
+#include "sim/full_system.hh"
using namespace AlphaISA;
}};
@@ -81,6 +82,7 @@
#include "cpu/exetrace.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/alpha/tlb.cc
--- a/src/arch/alpha/tlb.cc Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/alpha/tlb.cc Fri Sep 30 00:27:16 2011 -0700
@@ -42,6 +42,7 @@
#include "base/trace.hh"
#include "cpu/thread_context.hh"
#include "debug/TLB.hh"
+#include "sim/full_system.hh"
using namespace std;
@@ -370,7 +371,7 @@
TLB::translateInst(RequestPtr req, ThreadContext *tc)
{
//If this is a pal pc, then set PHYSICAL
- if (FULL_SYSTEM && PcPAL(req->getPC()))
+ if (FullSystem && PcPAL(req->getPC()))
req->setFlags(Request::PHYSICAL);
if (PcPAL(req->getPC())) {
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/faults.cc Fri Sep 30 00:27:16 2011 -0700
@@ -134,7 +134,7 @@
void
MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
setExceptionState(tc, code());
tc->pcState(vect(tc));
@@ -146,7 +146,7 @@
void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "%s encountered.\n", name());
/* All reset activity must be invoked from here */
Addr handler = vect(tc);
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/faults.hh Fri Sep 30 00:27:16 2011 -0700
@@ -38,6 +38,7 @@
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
#include "sim/faults.hh"
+#include "sim/full_system.hh"
namespace MipsISA
{
@@ -163,7 +164,7 @@
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
- if (FULL_SYSTEM) {
+ if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID;
tc->setMiscReg(MISCREG_CAUSE, cause);
@@ -197,7 +198,7 @@
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
MipsFault<T>::invoke(tc, inst);
- if (FULL_SYSTEM)
+ if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
}
};
@@ -249,7 +250,7 @@
invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
tc->pcState(this->vect(tc));
setTlbExceptionState(tc, this->code());
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/isa/decoder.isa
--- a/src/arch/mips/isa/decoder.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/isa/decoder.isa Fri Sep 30 00:27:16 2011 -0700
@@ -163,7 +163,7 @@
format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
- 0x4: decode FULL_SYSTEM {
+ 0x4: decode FullSystem {
0: syscall_se({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative);
default: syscall({{ fault = new SystemCallFault(); }});
@@ -212,7 +212,7 @@
0x0: add({{
IntReg result;
Rd = result = Rs + Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, Rt)) {
fault = new IntegerOverflowFault();
}
@@ -221,7 +221,7 @@
0x2: sub({{
IntReg result;
Rd = result = Rs - Rt;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, ~Rt)) {
fault = new IntegerOverflowFault();
}
@@ -325,7 +325,7 @@
0x0: addi({{
IntReg result;
Rt = result = Rs + imm;
- if (FULL_SYSTEM &&
+ if (FullSystem &&
findOverflow(32, result, Rs, imm)) {
fault = new IntegerOverflowFault();
}
@@ -2433,7 +2433,7 @@
}
}
0x3: decode OP default FailUnimpl::rdhwr() {
- 0x0: decode FULL_SYSTEM {
+ 0x0: decode FullSystem {
0: decode RD {
29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
}
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/isa/formats/control.isa
--- a/src/arch/mips/isa/formats/control.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/isa/formats/control.isa Fri Sep 30 00:27:16 2011 -0700
@@ -128,7 +128,7 @@
%(op_decl)s;
%(op_rd)s;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){
%(code)s;
@@ -176,7 +176,7 @@
bool
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{
- if (!FULL_SYSTEM)
+ if (!FullSystem)
return true;
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@@ -198,7 +198,7 @@
bool inline
isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible
@@ -215,7 +215,7 @@
isMMUTLB(%(CPU_exec_context)s *xc)
{
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
- return FULL_SYSTEM && (Config & 0x380) == 0x80;
+ return FullSystem && (Config & 0x380) == 0x80;
}
}};
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/isa/formats/dsp.isa
--- a/src/arch/mips/isa/formats/dsp.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/isa/formats/dsp.isa Fri Sep 30 00:27:16 2011 -0700
@@ -143,7 +143,7 @@
bool
isDspEnabled(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
}
}};
@@ -151,7 +151,7 @@
bool
isDspPresent(%(CPU_exec_context)s *xc)
{
- return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
+ return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
}
}};
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/isa/formats/fp.isa
--- a/src/arch/mips/isa/formats/fp.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/isa/formats/fp.isa Fri Sep 30 00:27:16 2011 -0700
@@ -174,7 +174,7 @@
//When is the right time to reset cause bits?
//start of every instruction or every cycle?
- if (FULL_SYSTEM)
+ if (FullSystem)
fpResetCauseBits(xc);
%(op_decl)s;
%(op_rd)s;
@@ -191,7 +191,7 @@
//Check for IEEE 754 FP Exceptions
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
bool invalid_op = false;
- if (FULL_SYSTEM) {
+ if (FullSystem) {
invalid_op =
fpInvalidOp((FPOp*)this, xc, Fd, traceData);
}
diff -r 30a97c4198df -r 66bf413b0d5b src/arch/mips/isa/formats/unimp.isa
--- a/src/arch/mips/isa/formats/unimp.isa Tue Sep 27 00:25:26 2011 -0700
+++ b/src/arch/mips/isa/formats/unimp.isa Fri Sep 30 00:27:16 2011 -0700
@@ -193,7 +193,7 @@
CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0))
return new CoprocessorUnusableFault(0);
else
@@ -210,7 +210,7 @@
CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const
{
- if (FULL_SYSTEM) {
+ if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1))
return new CoprocessorUnusableFault(1);
else
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
