changeset 925f15f96322 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=925f15f96322
description:
SE/FS: Build the devices in SE mode.
diffstat:
src/arch/sparc/isa_traits.hh | 4 -
src/base/vnc/SConscript | 8 +-
src/cpu/SConscript | 5 +-
src/cpu/intr_control.cc | 8 ++
src/dev/SConscript | 144 ++++++++++++++++++++--------------------
src/dev/alpha/AlphaBackdoor.py | 4 +-
src/dev/alpha/SConscript | 2 +-
src/dev/alpha/backdoor.cc | 11 ++-
src/dev/alpha/backdoor.hh | 2 +
src/dev/alpha/tsunami.cc | 2 +
src/dev/arm/SConscript | 2 +-
src/dev/arm/gic.cc | 1 +
src/dev/arm/realview.cc | 2 +
src/dev/mips/SConscript | 2 +-
src/dev/mips/malta.cc | 3 +
src/dev/mips/malta_cchip.cc | 1 +
src/dev/mips/malta_io.cc | 1 +
src/dev/mips/malta_pchip.cc | 1 +
src/dev/simple_disk.cc | 2 +
src/dev/sparc/SConscript | 2 +-
src/dev/sparc/iob.cc | 1 +
src/dev/sparc/t1000.cc | 2 +
src/dev/x86/SConscript | 2 +-
src/dev/x86/i82094aa.cc | 7 +
src/dev/x86/pc.cc | 2 +
25 files changed, 129 insertions(+), 92 deletions(-)
diffs (truncated from 571 to 300 lines):
diff -r 66bf413b0d5b -r 925f15f96322 src/arch/sparc/isa_traits.hh
--- a/src/arch/sparc/isa_traits.hh Fri Sep 30 00:27:16 2011 -0700
+++ b/src/arch/sparc/isa_traits.hh Fri Sep 30 00:28:33 2011 -0700
@@ -35,7 +35,6 @@
#include "arch/sparc/sparc_traits.hh"
#include "arch/sparc/types.hh"
#include "base/types.hh"
-#include "config/full_system.hh"
#include "cpu/static_inst_fwd.hh"
namespace BigEndianGuest {}
@@ -78,7 +77,6 @@
const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
const Addr BytesInPageMask = ULL(0x1FFF);
-#if FULL_SYSTEM
enum InterruptTypes
{
IT_TRAP_LEVEL_ZERO,
@@ -91,8 +89,6 @@
NumInterruptTypes
};
-#endif
-
// Memory accesses cannot be unaligned
const bool HasUnalignedMemAcc = false;
}
diff -r 66bf413b0d5b -r 925f15f96322 src/base/vnc/SConscript
--- a/src/base/vnc/SConscript Fri Sep 30 00:27:16 2011 -0700
+++ b/src/base/vnc/SConscript Fri Sep 30 00:28:33 2011 -0700
@@ -39,10 +39,8 @@
Import('*')
-if env['FULL_SYSTEM']:
- SimObject('VncServer.py')
- Source('vncserver.cc')
- DebugFlag('VNC')
-
Source('convert.cc')
+SimObject('VncServer.py')
+Source('vncserver.cc')
+DebugFlag('VNC')
diff -r 66bf413b0d5b -r 925f15f96322 src/cpu/SConscript
--- a/src/cpu/SConscript Fri Sep 30 00:27:16 2011 -0700
+++ b/src/cpu/SConscript Fri Sep 30 00:28:33 2011 -0700
@@ -109,6 +109,7 @@
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('IntelTrace.py')
+SimObject('IntrControl.py')
SimObject('NativeTrace.py')
Source('activity.cc')
@@ -118,6 +119,7 @@
Source('exetrace.cc')
Source('func_unit.cc')
Source('inteltrace.cc')
+Source('intr_control.cc')
Source('nativetrace.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
@@ -127,9 +129,6 @@
Source('thread_state.cc')
if env['FULL_SYSTEM']:
- SimObject('IntrControl.py')
-
- Source('intr_control.cc')
Source('profile.cc')
if env['TARGET_ISA'] == 'sparc':
diff -r 66bf413b0d5b -r 925f15f96322 src/cpu/intr_control.cc
--- a/src/cpu/intr_control.cc Fri Sep 30 00:27:16 2011 -0700
+++ b/src/cpu/intr_control.cc Fri Sep 30 00:28:33 2011 -0700
@@ -48,19 +48,27 @@
void
IntrControl::post(int cpu_id, int int_num, int index)
{
+#if FULL_SYSTEM
DPRINTF(IntrControl, "post %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->postInterrupt(int_num, index);
+#else
+ panic("Called IntrControl::post in SE mode.\n");
+#endif
}
void
IntrControl::clear(int cpu_id, int int_num, int index)
{
+#if FULL_SYSTEM
DPRINTF(IntrControl, "clear %d:%d (cpu %d)\n", int_num, index, cpu_id);
std::vector<ThreadContext *> &tcvec = sys->threadContexts;
BaseCPU *cpu = tcvec[cpu_id]->getCpuPtr();
cpu->clearInterrupt(int_num, index);
+#else
+ panic("Called IntrControl::clear in SE mode.\n");
+#endif
}
IntrControl *
diff -r 66bf413b0d5b -r 925f15f96322 src/dev/SConscript
--- a/src/dev/SConscript Fri Sep 30 00:27:16 2011 -0700
+++ b/src/dev/SConscript Fri Sep 30 00:28:33 2011 -0700
@@ -34,79 +34,77 @@
if env['TARGET_ISA'] == 'no':
Return()
-if env['FULL_SYSTEM']:
- SimObject('BadDevice.py')
- SimObject('CopyEngine.py')
- SimObject('Device.py')
- SimObject('DiskImage.py')
- SimObject('Ethernet.py')
- SimObject('Ide.py')
- SimObject('Pci.py')
- SimObject('Platform.py')
- SimObject('SimpleDisk.py')
- SimObject('Terminal.py')
- SimObject('Uart.py')
+SimObject('BadDevice.py')
+SimObject('CopyEngine.py')
+SimObject('Device.py')
+SimObject('DiskImage.py')
+SimObject('Ethernet.py')
+SimObject('Ide.py')
+SimObject('Pci.py')
+SimObject('Platform.py')
+SimObject('SimpleDisk.py')
+SimObject('Terminal.py')
+SimObject('Uart.py')
- Source('baddev.cc')
- Source('copy_engine.cc')
- Source('disk_image.cc')
- Source('etherbus.cc')
- Source('etherdevice.cc')
- Source('etherdump.cc')
- Source('etherint.cc')
- Source('etherlink.cc')
- Source('etherpkt.cc')
- Source('ethertap.cc')
- Source('i8254xGBe.cc')
- Source('ide_ctrl.cc')
- Source('ide_disk.cc')
- Source('intel_8254_timer.cc')
- Source('io_device.cc')
- Source('isa_fake.cc')
- Source('mc146818.cc')
- Source('ns_gige.cc')
- Source('pciconfigall.cc')
- Source('pcidev.cc')
- Source('pktfifo.cc')
- Source('platform.cc')
- Source('ps2.cc')
- Source('simple_disk.cc')
- Source('sinic.cc')
- Source('terminal.cc')
- Source('uart.cc')
- Source('uart8250.cc')
+Source('baddev.cc')
+Source('copy_engine.cc')
+Source('disk_image.cc')
+Source('etherbus.cc')
+Source('etherdevice.cc')
+Source('etherdump.cc')
+Source('etherint.cc')
+Source('etherlink.cc')
+Source('etherpkt.cc')
+Source('ethertap.cc')
+Source('i8254xGBe.cc')
+Source('ide_ctrl.cc')
+Source('ide_disk.cc')
+Source('intel_8254_timer.cc')
+Source('io_device.cc')
+Source('isa_fake.cc')
+Source('mc146818.cc')
+Source('ns_gige.cc')
+Source('pciconfigall.cc')
+Source('pcidev.cc')
+Source('pktfifo.cc')
+Source('platform.cc')
+Source('ps2.cc')
+Source('simple_disk.cc')
+Source('sinic.cc')
+Source('terminal.cc')
+Source('uart.cc')
+Source('uart8250.cc')
- DebugFlag('DiskImageRead')
- DebugFlag('DiskImageWrite')
- DebugFlag('DMA')
- DebugFlag('DMACopyEngine')
- DebugFlag('Ethernet')
- DebugFlag('EthernetCksum')
- DebugFlag('EthernetDMA')
- DebugFlag('EthernetData')
- DebugFlag('EthernetDesc')
- DebugFlag('EthernetEEPROM')
- DebugFlag('EthernetIntr')
- DebugFlag('EthernetPIO')
- DebugFlag('EthernetSM')
- DebugFlag('IdeCtrl')
- DebugFlag('IdeDisk')
- DebugFlag('Intel8254Timer')
- DebugFlag('IsaFake')
- DebugFlag('MC146818')
- DebugFlag('PCIDEV')
- DebugFlag('PciConfigAll')
- DebugFlag('SimpleDisk')
- DebugFlag('SimpleDiskData')
- DebugFlag('Terminal')
- DebugFlag('TerminalVerbose')
- DebugFlag('Uart')
+DebugFlag('DiskImageRead')
+DebugFlag('DiskImageWrite')
+DebugFlag('DMA')
+DebugFlag('DMACopyEngine')
+DebugFlag('Ethernet')
+DebugFlag('EthernetCksum')
+DebugFlag('EthernetDMA')
+DebugFlag('EthernetData')
+DebugFlag('EthernetDesc')
+DebugFlag('EthernetEEPROM')
+DebugFlag('EthernetIntr')
+DebugFlag('EthernetPIO')
+DebugFlag('EthernetSM')
+DebugFlag('IdeCtrl')
+DebugFlag('IdeDisk')
+DebugFlag('Intel8254Timer')
+DebugFlag('IsaFake')
+DebugFlag('MC146818')
+DebugFlag('PCIDEV')
+DebugFlag('PciConfigAll')
+DebugFlag('SimpleDisk')
+DebugFlag('SimpleDiskData')
+DebugFlag('Terminal')
+DebugFlag('TerminalVerbose')
+DebugFlag('Uart')
- CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
- CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
- 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
- 'EthernetCksum', 'EthernetEEPROM' ])
- CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
- 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
- CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
-
+CompoundFlag('DiskImageAll', [ 'DiskImageRead', 'DiskImageWrite' ])
+CompoundFlag('EthernetAll', [ 'Ethernet', 'EthernetPIO', 'EthernetDMA',
+ 'EthernetData' , 'EthernetDesc', 'EthernetIntr', 'EthernetSM',
+ 'EthernetCksum', 'EthernetEEPROM' ])
+CompoundFlag('EthernetNoData', [ 'Ethernet', 'EthernetPIO', 'EthernetDesc',
+ 'EthernetIntr', 'EthernetSM', 'EthernetCksum' ])
+CompoundFlag('IdeAll', [ 'IdeCtrl', 'IdeDisk' ])
diff -r 66bf413b0d5b -r 925f15f96322 src/dev/alpha/AlphaBackdoor.py
--- a/src/dev/alpha/AlphaBackdoor.py Fri Sep 30 00:27:16 2011 -0700
+++ b/src/dev/alpha/AlphaBackdoor.py Fri Sep 30 00:28:33 2011 -0700
@@ -26,6 +26,7 @@
#
# Authors: Nathan Binkert
+from m5.defines import buildEnv
from m5.params import *
from m5.proxy import *
from Device import BasicPioDevice
@@ -35,4 +36,5 @@
cpu = Param.BaseCPU(Parent.cpu[0], "Processor")
disk = Param.SimpleDisk("Simple Disk")
terminal = Param.Terminal(Parent.any, "The console terminal")
- system = Param.AlphaSystem(Parent.any, "system object")
+ if buildEnv['FULL_SYSTEM']: # No AlphaSystem in SE mode.
+ system = Param.AlphaSystem(Parent.any, "system object")
diff -r 66bf413b0d5b -r 925f15f96322 src/dev/alpha/SConscript
--- a/src/dev/alpha/SConscript Fri Sep 30 00:27:16 2011 -0700
+++ b/src/dev/alpha/SConscript Fri Sep 30 00:28:33 2011 -0700
@@ -31,7 +31,7 @@
Import('*')
-if env['FULL_SYSTEM'] and env['TARGET_ISA'] == 'alpha':
+if env['TARGET_ISA'] == 'alpha':
SimObject('AlphaBackdoor.py')
SimObject('Tsunami.py')
diff -r 66bf413b0d5b -r 925f15f96322 src/dev/alpha/backdoor.cc
--- a/src/dev/alpha/backdoor.cc Fri Sep 30 00:27:16 2011 -0700
+++ b/src/dev/alpha/backdoor.cc Fri Sep 30 00:28:33 2011 -0700
@@ -38,7 +38,11 @@
#include <cstddef>
#include <string>
+#include "config/full_system.hh"
+
+#if FULL_SYSTEM //XXX No AlphaSystem in SE mode.
#include "arch/alpha/system.hh"
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