[gem5-dev] changeset in gem5: SPARC: Turn on handleIprRead and handleIprWri...

[Gabe Black]

changeset 01be402c5bf1 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=01be402c5bf1
description:
        SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.

diffstat:

 src/arch/sparc/mmapped_ipr.hh |  8 --------
 src/arch/sparc/tlb.cc         |  4 ----
 src/arch/sparc/tlb.hh         |  2 --
 3 files changed, 0 insertions(+), 14 deletions(-)

diffs (60 lines):

diff -r 017e5bbbb4e2 -r 01be402c5bf1 src/arch/sparc/mmapped_ipr.hh
--- a/src/arch/sparc/mmapped_ipr.hh     Sun Oct 09 23:48:27 2011 -0700
+++ b/src/arch/sparc/mmapped_ipr.hh     Mon Oct 10 00:31:51 2011 -0700
@@ -48,21 +48,13 @@
 inline Tick
 handleIprRead(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegRead(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 inline Tick
 handleIprWrite(ThreadContext *xc, Packet *pkt)
 {
-#if FULL_SYSTEM
     return xc->getDTBPtr()->doMmuRegWrite(xc, pkt);
-#else
-    panic("Shouldn't have a memory mapped register in SE\n");
-#endif
 }
 
 
diff -r 017e5bbbb4e2 -r 01be402c5bf1 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc     Sun Oct 09 23:48:27 2011 -0700
+++ b/src/arch/sparc/tlb.cc     Mon Oct 10 00:31:51 2011 -0700
@@ -840,8 +840,6 @@
     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
 }
 
-#if FULL_SYSTEM
-
 Tick
 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
 {
@@ -1280,8 +1278,6 @@
     return tc->getCpuPtr()->ticks(1);
 }
 
-#endif
-
 void
 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
 {
diff -r 017e5bbbb4e2 -r 01be402c5bf1 src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh     Sun Oct 09 23:48:27 2011 -0700
+++ b/src/arch/sparc/tlb.hh     Mon Oct 10 00:31:51 2011 -0700
@@ -167,10 +167,8 @@
     Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
     void translateTiming(RequestPtr req, ThreadContext *tc,
             Translation *translation, Mode mode);
-#if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing
_______________________________________________
gem5-dev mailing list
gem5-dev@gem5.org
http://m5sim.org/mailman/listinfo/gem5-dev