changeset 509e9bb84dfa in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=509e9bb84dfa
description:
SE/FS: Turn on the page table class in FS.
diffstat:
src/arch/mips/pagetable.hh | 53 +++++++++++++++++++++++++-------------------
src/arch/mips/tlb.hh | 27 ----------------------
src/mem/SConscript | 4 +--
src/mem/page_table.cc | 25 ++++++++++++++++-----
src/mem/page_table.hh | 11 ++++++++-
src/mem/translating_port.cc | 14 +----------
src/mem/translating_port.hh | 4 +-
7 files changed, 64 insertions(+), 74 deletions(-)
diffs (truncated from 361 to 300 lines):
diff -r c77d9ef26d2b -r 509e9bb84dfa src/arch/mips/pagetable.hh
--- a/src/arch/mips/pagetable.hh Sun Oct 16 05:06:40 2011 -0700
+++ b/src/arch/mips/pagetable.hh Sun Oct 16 05:06:40 2011 -0700
@@ -34,34 +34,14 @@
#ifndef __ARCH_MIPS_PAGETABLE_H__
#define __ARCH_MIPS_PAGETABLE_H__
-#include "arch/mips/isa_traits.hh"
-#include "arch/mips/utility.hh"
-#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
+#include "base/misc.hh"
+#include "base/types.hh"
+#include "sim/serialize.hh"
namespace MipsISA {
struct VAddr
{
- static const int ImplBits = 43;
- static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
- static const Addr UnImplMask = ~ImplMask;
-
- VAddr(Addr a) : addr(a) {}
- Addr addr;
- operator Addr() const { return addr; }
- const VAddr &operator=(Addr a) { addr = a; return *this; }
-
- Addr vpn() const { return (addr & ImplMask) >> PageShift; }
- Addr page() const { return addr & Page_Mask; }
- Addr offset() const { return addr & PageOffset; }
-
- Addr level3() const
- { return MipsISA::PteAddr(addr >> PageShift); }
- Addr level2() const
- { return MipsISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
- Addr level1() const
- { return MipsISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry
@@ -98,6 +78,33 @@
void unserialize(Checkpoint *cp, const std::string §ion);
};
+// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
+struct TlbEntry
+{
+ Addr _pageStart;
+ TlbEntry() {}
+ TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
+
+ Addr pageStart()
+ {
+ return _pageStart;
+ }
+
+ void
+ updateVaddr(Addr new_vaddr) {}
+
+ void serialize(std::ostream &os)
+ {
+ SERIALIZE_SCALAR(_pageStart);
+ }
+
+ void unserialize(Checkpoint *cp, const std::string §ion)
+ {
+ UNSERIALIZE_SCALAR(_pageStart);
+ }
+
+};
+
};
#endif // __ARCH_MIPS_PAGETABLE_H__
diff -r c77d9ef26d2b -r 509e9bb84dfa src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh Sun Oct 16 05:06:40 2011 -0700
+++ b/src/arch/mips/tlb.hh Sun Oct 16 05:06:40 2011 -0700
@@ -55,33 +55,6 @@
simply create an ITLB and DTLB that will point to the real TLB */
namespace MipsISA {
-// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-struct TlbEntry
-{
- Addr _pageStart;
- TlbEntry() {}
- TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
-
- Addr pageStart()
- {
- return _pageStart;
- }
-
- void
- updateVaddr(Addr new_vaddr) {}
-
- void serialize(std::ostream &os)
- {
- SERIALIZE_SCALAR(_pageStart);
- }
-
- void unserialize(Checkpoint *cp, const std::string §ion)
- {
- UNSERIALIZE_SCALAR(_pageStart);
- }
-
-};
-
class TLB : public BaseTLB
{
protected:
diff -r c77d9ef26d2b -r 509e9bb84dfa src/mem/SConscript
--- a/src/mem/SConscript Sun Oct 16 05:06:40 2011 -0700
+++ b/src/mem/SConscript Sun Oct 16 05:06:40 2011 -0700
@@ -46,12 +46,10 @@
if env['TARGET_ISA'] != 'no':
SimObject('PhysicalMemory.py')
Source('dram.cc')
+ Source('page_table.cc')
Source('physical.cc')
Source('translating_port.cc')
-if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no':
- Source('page_table.cc')
-
DebugFlag('Bus')
DebugFlag('BusAddrRanges')
DebugFlag('BusBridge')
diff -r c77d9ef26d2b -r 509e9bb84dfa src/mem/page_table.cc
--- a/src/mem/page_table.cc Sun Oct 16 05:06:40 2011 -0700
+++ b/src/mem/page_table.cc Sun Oct 16 05:06:40 2011 -0700
@@ -52,9 +52,15 @@
using namespace std;
using namespace TheISA;
-PageTable::PageTable(Process *_process, Addr _pageSize)
- : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
- process(_process)
+PageTable::PageTable(
+#if !FULL_SYSTEM
+ Process *_process,
+#endif
+ Addr _pageSize)
+ : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize)))
+#if !FULL_SYSTEM
+ , process(_process)
+#endif
{
assert(isPowerOf2(pageSize));
pTableCache[0].vaddr = 0;
@@ -83,9 +89,11 @@
vaddr);
}
+#if !FULL_SYSTEM
pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr,
process->system->new_page());
updateCache(vaddr, pTable[vaddr]);
+#endif
}
}
@@ -196,7 +204,9 @@
PTableItr iter = pTable.begin();
PTableItr end = pTable.end();
while (iter != end) {
+#if !FULL_SYSTEM
os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n";
+#endif
paramOut(os, "vaddr", iter->first);
iter->second.serialize(os);
@@ -212,17 +222,20 @@
{
int i = 0, count;
paramIn(cp, section, "ptable.size", count);
- Addr vaddr;
- TheISA::TlbEntry *entry;
pTable.clear();
- while(i < count) {
+ while (i < count) {
+#if !FULL_SYSTEM
+ TheISA::TlbEntry *entry;
+ Addr vaddr;
+
paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr",
vaddr);
entry = new TheISA::TlbEntry();
entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i));
pTable[vaddr] = *entry;
++i;
+#endif
}
}
diff -r c77d9ef26d2b -r 509e9bb84dfa src/mem/page_table.hh
--- a/src/mem/page_table.hh Sun Oct 16 05:06:40 2011 -0700
+++ b/src/mem/page_table.hh Sun Oct 16 05:06:40 2011 -0700
@@ -42,11 +42,14 @@
#include "arch/tlb.hh"
#include "base/hashmap.hh"
#include "base/types.hh"
+#include "config/full_system.hh"
#include "config/the_isa.hh"
#include "mem/request.hh"
#include "sim/serialize.hh"
+#if !FULL_SYSTEM
class Process;
+#endif
/**
* Page Table Declaration.
@@ -68,11 +71,17 @@
const Addr pageSize;
const Addr offsetMask;
+#if !FULL_SYSTEM
Process *process;
+#endif
public:
- PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize);
+ PageTable(
+#if !FULL_SYSTEM
+ Process *_process,
+#endif
+ Addr _pageSize = TheISA::VMPageSize);
~PageTable();
diff -r c77d9ef26d2b -r 509e9bb84dfa src/mem/translating_port.cc
--- a/src/mem/translating_port.cc Sun Oct 16 05:06:40 2011 -0700
+++ b/src/mem/translating_port.cc Sun Oct 16 05:06:40 2011 -0700
@@ -35,9 +35,7 @@
#include "base/chunk_generator.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
-#endif
#include "mem/port.hh"
#include "mem/translating_port.hh"
#if !FULL_SYSTEM
@@ -67,14 +65,12 @@
int prevSize = 0;
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-#if !FULL_SYSTEM
Addr paddr;
if (!pTable->translate(gen.addr(),paddr))
return false;
Port::readBlob(paddr, p + prevSize, gen.size());
-#endif
prevSize += gen.size();
}
@@ -95,7 +91,6 @@
int prevSize = 0;
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-#if !FULL_SYSTEM
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
@@ -104,9 +99,11 @@
VMPageSize);
} else if (allocating == NextPage) {
// check if we've accessed the next page on the stack
+#if !FULL_SYSTEM
if (!process->fixupStackFault(gen.addr()))
panic("Page table fault when accessing virtual address %#x
"
"during functional write\n", gen.addr());
+#endif
} else {
return false;
}
@@ -114,7 +111,6 @@
}
Port::writeBlob(paddr, p + prevSize, gen.size());
-#endif
prevSize += gen.size();
}
@@ -133,7 +129,6 @@
TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size)
{
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
-#if !FULL_SYSTEM
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
@@ -146,7 +141,6 @@
}
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
