changeset 1e3ca5d77b53 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1e3ca5d77b53
description:
SE/FS: Get rid of FULL_SYSTEM in MIPS.
diffstat:
src/arch/mips/BISystem.py | 11 ++++----
src/arch/mips/MipsSystem.py | 25 +++++++++----------
src/arch/mips/SConscript | 23 ++++++++----------
src/arch/mips/faults.cc | 3 --
src/arch/mips/isa_traits.hh | 1 -
src/arch/mips/linux/system.cc | 7 +++--
src/arch/mips/mips_core_specific.cc | 46 -------------------------------------
src/arch/mips/mips_core_specific.hh | 42 ---------------------------------
src/arch/mips/remote_gdb.cc | 10 ++++----
src/arch/mips/stacktrace.cc | 1 +
src/arch/mips/system.cc | 7 +----
src/arch/mips/system.hh | 7 +----
src/arch/mips/utility.cc | 23 ++++--------------
src/arch/mips/utility.hh | 1 +
src/dev/mips/malta_cchip.cc | 1 -
15 files changed, 45 insertions(+), 163 deletions(-)
diffs (truncated from 461 to 300 lines):
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/BISystem.py
--- a/src/arch/mips/BISystem.py Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/BISystem.py Sun Oct 30 18:39:38 2011 -0700
@@ -32,10 +32,9 @@
from System import *
-if buildEnv['FULL_SYSTEM']:
- class BareIronMipsSystem(MipsSystem):
- type = 'BareIronMipsSystem'
- system_type = 34
- system_rev = 1 << 10
- hex_file_name = Param.String('test.hex',"hex file that contains
[address,data] pairs")
+class BareIronMipsSystem(MipsSystem):
+ type = 'BareIronMipsSystem'
+ system_type = 34
+ system_rev = 1 << 10
+ hex_file_name = Param.String('test.hex',"hex file that contains
[address,data] pairs")
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/MipsSystem.py
--- a/src/arch/mips/MipsSystem.py Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/MipsSystem.py Sun Oct 30 18:39:38 2011 -0700
@@ -43,19 +43,18 @@
system_rev = Param.UInt64("Revision of system we are emulating")
load_addr_mask = 0xffffffffff
-if buildEnv['FULL_SYSTEM']:
- class LinuxMipsSystem(MipsSystem):
- type = 'LinuxMipsSystem'
- system_type = 34
- system_rev = 1 << 10
+class LinuxMipsSystem(MipsSystem):
+ type = 'LinuxMipsSystem'
+ system_type = 34
+ system_rev = 1 << 10
- boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
- "boot processor frequency")
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ "boot processor frequency")
- class BareIronMipsSystem(MipsSystem):
- type = 'BareIronMipsSystem'
- bare_iron = True
- system_type = 34
- system_rev = 1 << 10
- hex_file_name = Param.String('test.hex',"hex file that contains
[address,data] pairs")
+class BareIronMipsSystem(MipsSystem):
+ type = 'BareIronMipsSystem'
+ bare_iron = True
+ system_type = 34
+ system_rev = 1 << 10
+ hex_file_name = Param.String('test.hex',"hex file that contains
[address,data] pairs")
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/SConscript
--- a/src/arch/mips/SConscript Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/SConscript Sun Oct 30 18:39:38 2011 -0700
@@ -33,32 +33,29 @@
Import('*')
if env['TARGET_ISA'] == 'mips':
+ Source('bare_iron/system.cc')
Source('dsp.cc')
Source('faults.cc')
+ Source('idle_event.cc')
Source('interrupts.cc')
Source('isa.cc')
+ Source('linux/linux.cc')
+ Source('linux/process.cc')
+ Source('linux/system.cc')
Source('pagetable.cc')
+ Source('process.cc')
Source('remote_gdb.cc')
+ Source('stacktrace.cc')
+ Source('system.cc')
Source('tlb.cc')
Source('utility.cc')
Source('vtophys.cc')
SimObject('MipsInterrupts.py')
- DebugFlag('MipsPRA')
+ SimObject('MipsSystem.py')
SimObject('MipsTLB.py')
- if env['FULL_SYSTEM']:
- SimObject('MipsSystem.py')
- Source('idle_event.cc')
- Source('mips_core_specific.cc')
- Source('system.cc')
- Source('stacktrace.cc')
- Source('linux/system.cc')
- Source('bare_iron/system.cc')
- else:
- Source('process.cc')
- Source('linux/linux.cc')
- Source('linux/process.cc')
+ DebugFlag('MipsPRA')
# Add in files generated by the ISA description.
isa_desc_files = env.ISADesc('isa/main.isa')
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/faults.cc Sun Oct 30 18:39:38 2011 -0700
@@ -37,11 +37,8 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh"
-
-#if !FULL_SYSTEM
#include "mem/page_table.hh"
#include "sim/process.hh"
-#endif
namespace MipsISA
{
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/isa_traits.hh
--- a/src/arch/mips/isa_traits.hh Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/isa_traits.hh Sun Oct 30 18:39:38 2011 -0700
@@ -34,7 +34,6 @@
#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
#define __ARCH_MIPS_ISA_TRAITS_HH__
-#include "arch/mips/mips_core_specific.hh"
#include "arch/mips/types.hh"
#include "base/types.hh"
#include "config/full_system.hh"
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/linux/system.cc
--- a/src/arch/mips/linux/system.cc Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/linux/system.cc Sun Oct 30 18:39:38 2011 -0700
@@ -47,6 +47,7 @@
#include "base/loader/symtab.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
+#include "debug/Thread.hh"
#include "dev/platform.hh"
#include "kern/linux/events.hh"
#include "kern/linux/printk.hh"
@@ -76,7 +77,7 @@
* Since we aren't using a bootloader, we have to copy the
* kernel arguments directly into the kernel's memory.
*/
- virtPort.writeBlob(CommandLine(), (uint8_t*)params()->boot_osflags.c_str(),
+ virtPort->writeBlob(CommandLine(),
(uint8_t*)params()->boot_osflags.c_str(),
params()->boot_osflags.length()+1);
/**
@@ -85,7 +86,7 @@
* calculated it by using the PIT, RTC, etc.
*/
if (kernelSymtab->findAddress("est_cycle_freq", addr))
- virtPort.write(addr, (uint64_t)(SimClock::Frequency /
+ virtPort->write(addr, (uint64_t)(SimClock::Frequency /
p->boot_cpu_frequency));
/**
@@ -95,7 +96,7 @@
* 255 ASNs.
*/
if (kernelSymtab->findAddress("dp264_mv", addr))
- virtPort.write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
+ virtPort->write(addr + 0x18, LittleEndianGuest::htog((uint32_t)127));
else
panic("could not find dp264_mv\n");
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/mips_core_specific.cc
--- a/src/arch/mips/mips_core_specific.cc Sun Oct 30 17:38:11 2011 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2002, 2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- * Steve Reinhardt
- */
-
-#include "config/full_system.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
-
-#if FULL_SYSTEM
-
-////////////////////////////////////////////////////////////////////////
-//
-// Machine dependent functions
-//
-void
-MipsISA::initCPU(ThreadContext *tc, int cpuId)
-{}
-
-#endif // FULL_SYSTEM || BARE_IRON
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/mips_core_specific.hh
--- a/src/arch/mips/mips_core_specific.hh Sun Oct 30 17:38:11 2011 -0700
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2007 MIPS Technologies, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Jaidev Patwardhan
- */
-
-#ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
-#define __ARCH_MIPS_CORE_SPECIFIC_HH__
-
-#include "arch/mips/isa_traits.hh"
-
-class ThreadContext;
-
-namespace MipsISA {
- void initCPU(ThreadContext *tc, int cpuId);
-};
-
-#endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/remote_gdb.cc
--- a/src/arch/mips/remote_gdb.cc Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/remote_gdb.cc Sun Oct 30 18:39:38 2011 -0700
@@ -137,12 +137,12 @@
#include "arch/mips/remote_gdb.hh"
#include "arch/mips/vtophys.hh"
-#include "config/full_system.hh"
#include "cpu/decode.hh"
#include "cpu/thread_state.hh"
#include "debug/GDBAcc.hh"
#include "debug/GDBMisc.hh"
#include "mem/page_table.hh"
+#include "sim/full_system.hh"
using namespace std;
using namespace MipsISA;
@@ -158,13 +158,13 @@
bool
RemoteGDB::acc(Addr va, size_t len)
{
-#if FULL_SYSTEM
- panic("acc not implemented for MIPS FS!");
-#endif
TlbEntry entry;
//Check to make sure the first byte is mapped into the processes address
//space.
- return context->getProcessPtr()->pTable->lookup(va, entry);
+ if (FullSystem)
+ panic("acc not implemented for MIPS FS!");
+ else
+ return context->getProcessPtr()->pTable->lookup(va, entry);
}
/*
diff -r 232b5574d9c3 -r 1e3ca5d77b53 src/arch/mips/stacktrace.cc
--- a/src/arch/mips/stacktrace.cc Sun Oct 30 17:38:11 2011 -0700
+++ b/src/arch/mips/stacktrace.cc Sun Oct 30 18:39:38 2011 -0700
@@ -37,6 +37,7 @@
#include "base/trace.hh"
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