changeset 1a84c6a81299 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1a84c6a81299
description:
SE/FS: Make SE vs. FS mode a runtime parameter.
diffstat:
configs/common/FSConfig.py | 4 ++--
configs/example/fs.py | 4 ++--
configs/example/memtest.py | 2 +-
configs/example/ruby_direct_test.py | 2 +-
configs/example/ruby_fs.py | 2 +-
configs/example/ruby_mem_test.py | 2 +-
configs/example/ruby_network_test.py | 2 +-
configs/example/ruby_random_test.py | 2 +-
configs/example/se.py | 2 +-
configs/splash2/cluster.py | 2 +-
configs/splash2/run.py | 2 +-
src/sim/Root.py | 3 +++
src/sim/full_system.hh | 4 +---
src/sim/root.cc | 5 +++++
tests/configs/inorder-timing.py | 2 +-
tests/configs/memtest-ruby.py | 2 +-
tests/configs/memtest.py | 2 +-
tests/configs/o3-timing-mp-ruby.py | 2 +-
tests/configs/o3-timing-mp.py | 2 +-
tests/configs/o3-timing-ruby.py | 2 +-
tests/configs/o3-timing.py | 2 +-
tests/configs/pc-o3-timing.py | 2 +-
tests/configs/pc-simple-atomic.py | 2 +-
tests/configs/pc-simple-timing.py | 2 +-
tests/configs/realview-o3-dual.py | 2 +-
tests/configs/realview-o3.py | 2 +-
tests/configs/realview-simple-atomic-dual.py | 2 +-
tests/configs/realview-simple-atomic.py | 2 +-
tests/configs/realview-simple-timing-dual.py | 2 +-
tests/configs/realview-simple-timing.py | 2 +-
tests/configs/rubytest-ruby.py | 2 +-
tests/configs/simple-atomic-mp-ruby.py | 2 +-
tests/configs/simple-atomic-mp.py | 2 +-
tests/configs/simple-atomic.py | 2 +-
tests/configs/simple-timing-mp-ruby.py | 2 +-
tests/configs/simple-timing-mp.py | 2 +-
tests/configs/simple-timing-ruby.py | 2 +-
tests/configs/simple-timing.py | 2 +-
tests/configs/t1000-simple-atomic.py | 2 +-
tests/configs/tsunami-inorder.py | 2 +-
tests/configs/tsunami-o3-dual.py | 2 +-
tests/configs/tsunami-o3.py | 2 +-
tests/configs/tsunami-simple-atomic-dual.py | 2 +-
tests/configs/tsunami-simple-atomic.py | 2 +-
tests/configs/tsunami-simple-timing-dual.py | 2 +-
tests/configs/tsunami-simple-timing.py | 2 +-
tests/configs/twosys-tsunami-simple-atomic.py | 2 +-
47 files changed, 55 insertions(+), 49 deletions(-)
diffs (truncated from 551 to 300 lines):
diff -r 1882c44e510a -r 1a84c6a81299 configs/common/FSConfig.py
--- a/configs/common/FSConfig.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/common/FSConfig.py Sat Jan 28 07:24:34 2012 -0800
@@ -552,8 +552,8 @@
return self
-def makeDualRoot(testSystem, driveSystem, dumpfile):
- self = Root()
+def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
+ self = Root(full_system = full_system)
self.testsys = testSystem
self.drivesys = driveSystem
self.etherlink = EtherLink()
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/fs.py
--- a/configs/example/fs.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/fs.py Sat Jan 28 07:24:34 2012 -0800
@@ -198,9 +198,9 @@
drive_sys.kernel = binary(options.kernel)
drive_sys.init_param = options.init_param
- root = makeDualRoot(test_sys, drive_sys, options.etherdump)
+ root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
elif len(bm) == 1:
- root = Root(system=test_sys)
+ root = Root(full_system=True, system=test_sys)
else:
print "Error I don't know how to create more than 2 systems."
sys.exit(1)
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/memtest.py
--- a/configs/example/memtest.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/memtest.py Sat Jan 28 07:24:34 2012 -0800
@@ -172,7 +172,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
if options.atomic:
root.system.mem_mode = 'atomic'
else:
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/ruby_direct_test.py Sat Jan 28 07:24:34 2012 -0800
@@ -111,7 +111,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/ruby_fs.py Sat Jan 28 07:24:34 2012 -0800
@@ -141,6 +141,6 @@
cpu.interrupts.pio = system.piobus.port
cpu.interrupts.int_port = system.piobus.port
-root = Root(system = system)
+root = Root(full_system = True, system = system)
Simulation.run(options, root, system, FutureClass)
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/ruby_mem_test.py Sat Jan 28 07:24:34 2012 -0800
@@ -162,7 +162,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/ruby_network_test.py Sat Jan 28 07:24:34 2012 -0800
@@ -121,7 +121,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/ruby_random_test.py Sat Jan 28 07:24:34 2012 -0800
@@ -131,7 +131,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
diff -r 1882c44e510a -r 1a84c6a81299 configs/example/se.py
--- a/configs/example/se.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/example/se.py Sat Jan 28 07:24:34 2012 -0800
@@ -200,6 +200,6 @@
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
-root = Root(system = system)
+root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
diff -r 1882c44e510a -r 1a84c6a81299 configs/splash2/cluster.py
--- a/configs/splash2/cluster.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/splash2/cluster.py Sat Jan 28 07:24:34 2012 -0800
@@ -239,7 +239,7 @@
# Define the root
# ----------------------
-root = Root(system = system)
+root = Root(full_system = False, system = system)
# --------------------
# Pick the correct Splash2 Benchmarks
diff -r 1882c44e510a -r 1a84c6a81299 configs/splash2/run.py
--- a/configs/splash2/run.py Sat Jan 28 07:24:23 2012 -0800
+++ b/configs/splash2/run.py Sat Jan 28 07:24:34 2012 -0800
@@ -225,7 +225,7 @@
# Define the root
# ----------------------
-root = Root(system = system)
+root = Root(full_system = False, system = system)
# --------------------
# Pick the correct Splash2 Benchmarks
diff -r 1882c44e510a -r 1a84c6a81299 src/sim/Root.py
--- a/src/sim/Root.py Sat Jan 28 07:24:23 2012 -0800
+++ b/src/sim/Root.py Sat Jan 28 07:24:34 2012 -0800
@@ -28,6 +28,7 @@
# Authors: Nathan Binkert
from m5.SimObject import SimObject
+from m5.defines import buildEnv
from m5.params import *
from m5.util import fatal
@@ -58,6 +59,8 @@
type = 'Root'
+ full_system = Param.Bool("if this is a full system simulation")
+
# Time syncing prevents the simulation from running faster than real time.
time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
time_sync_period = Param.Clock("100ms", "how often to sync with real time")
diff -r 1882c44e510a -r 1a84c6a81299 src/sim/full_system.hh
--- a/src/sim/full_system.hh Sat Jan 28 07:24:23 2012 -0800
+++ b/src/sim/full_system.hh Sat Jan 28 07:24:34 2012 -0800
@@ -31,8 +31,6 @@
#ifndef __SIM_FULL_SYSTEM_HH__
#define __SIM_FULL_SYSTEM_HH__
-#include "config/full_system.hh"
-
-static const bool FullSystem = FULL_SYSTEM;
+extern bool FullSystem;
#endif // __SIM_FULL_SYSTEM_HH__
diff -r 1882c44e510a -r 1a84c6a81299 src/sim/root.cc
--- a/src/sim/root.cc Sat Jan 28 07:24:23 2012 -0800
+++ b/src/sim/root.cc Sat Jan 28 07:24:34 2012 -0800
@@ -33,6 +33,7 @@
#include "base/misc.hh"
#include "debug/TimeSync.hh"
+#include "sim/full_system.hh"
#include "sim/root.hh"
Root *Root::_root = NULL;
@@ -123,6 +124,8 @@
timeSyncEnable(params()->time_sync_enable);
}
+bool FullSystem;
+
Root *
RootParams::create()
{
@@ -132,5 +135,7 @@
created = true;
+ FullSystem = full_system;
+
return new Root(this);
}
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/inorder-timing.py Sat Jan 28 07:24:34 2012 -0800
@@ -54,4 +54,4 @@
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/memtest-ruby.py Sat Jan 28 07:24:34 2012 -0800
@@ -117,7 +117,7 @@
# run simulation
# -----------------------
-root = Root(system = system)
+root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
# Not much point in this being higher than the L1 latency
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/memtest.py
--- a/tests/configs/memtest.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/memtest.py Sat Jan 28 07:24:34 2012 -0800
@@ -86,7 +86,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
#root.trace.flags="Cache CachePort MemoryAccess"
#root.trace.cycle=1
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/o3-timing-mp-ruby.py Sat Jan 28 07:24:34 2012 -0800
@@ -51,5 +51,5 @@
# run simulation
# -----------------------
-root = Root(system = system)
+root = Root(full_system = False, system = system)
root.system.mem_mode = 'timing'
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/o3-timing-mp.py Sat Jan 28 07:24:34 2012 -0800
@@ -86,7 +86,7 @@
# run simulation
# -----------------------
-root = Root( system = system )
+root = Root( full_system = False, system = system )
root.system.mem_mode = 'timing'
#root.trace.flags="Bus Cache"
#root.trace.flags = "BusAddrRanges"
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/o3-timing-ruby.py Sat Jan 28 07:24:34 2012 -0800
@@ -43,4 +43,4 @@
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/o3-timing.py Sat Jan 28 07:24:34 2012 -0800
@@ -54,4 +54,4 @@
system.physmem.port = system.membus.port
cpu.connectAllPorts(system.membus)
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/pc-o3-timing.py Sat Jan 28 07:24:34 2012 -0800
@@ -108,6 +108,6 @@
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
-root = Root(system=system)
+root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('1THz')
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/pc-simple-atomic.py Sat Jan 28 07:24:34 2012 -0800
@@ -110,6 +110,6 @@
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
-root = Root(system=system)
+root = Root(full_system=True, system=system)
m5.ticks.setGlobalFrequency('1THz')
diff -r 1882c44e510a -r 1a84c6a81299 tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py Sat Jan 28 07:24:23 2012 -0800
+++ b/tests/configs/pc-simple-timing.py Sat Jan 28 07:24:34 2012 -0800
@@ -110,6 +110,6 @@
cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz'
-root = Root(system=system)
+root = Root(full_system=True, system=system)
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