changeset 00f0d0230596 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=00f0d0230596
description:
configs: More fixes for the memory system updates
diffstat:
configs/example/fs.py | 4 ++++
src/dev/arm/RealView.py | 4 ++--
2 files changed, 6 insertions(+), 2 deletions(-)
diffs (38 lines):
diff -r bb10807da889 -r 00f0d0230596 configs/example/fs.py
--- a/configs/example/fs.py Tue Jan 31 22:40:08 2012 -0800
+++ b/configs/example/fs.py Wed Feb 01 09:48:28 2012 -0800
@@ -193,6 +193,10 @@
drive_sys.cpu.physmem_port = drive_sys.physmem.port
if options.kernel is not None:
drive_sys.kernel = binary(options.kernel)
+ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
+ ranges = [AddrRange(bm[1].mem())])
+ drive_sys.iobridge.slave = drive_sys.iobus.port
+ drive_sys.iobridge.master = drive_sys.membus.port
drive_sys.init_param = options.init_param
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
diff -r bb10807da889 -r 00f0d0230596 src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py Tue Jan 31 22:40:08 2012 -0800
+++ b/src/dev/arm/RealView.py Wed Feb 01 09:48:28 2012 -0800
@@ -351,10 +351,11 @@
def attachOnChipIO(self, bus, bridge):
self.gic.pio = bus.port
self.a9scu.pio = bus.port
+ self.local_cpu_timer.pio = bus.port
# Bridge ranges based on excluding what is part of on-chip I/O
# (gic, a9scu)
bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
- AddrRange(self.local_cpu_timer.pio_addr, Addr.max)]
+ AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
# Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the
@@ -363,7 +364,6 @@
self.elba_uart.pio = bus.port
self.uart.pio = bus.port
self.realview_io.pio = bus.port
- self.local_cpu_timer.pio = bus.port
self.v2m_timer0.pio = bus.port
self.v2m_timer1.pio = bus.port
self.elba_timer0.pio = bus.port
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