> On Feb. 2, 2012, 12:51 a.m., Gabe Black wrote: > > src/cpu/o3/fetch_impl.hh, line 719 > > <http://reviews.gem5.org/r/1019/diff/1/?file=21619#file21619line719> > > > > Should this really be unconditionally set to true? If we at a commit > > point (if delayedCommit is false) then it's ok to take an interrupt there > > even if we're squashing. Or am I misunderstanding how this code works?
This flag is true if the last microop fetched was marked delayed commit. If the microops are being squashed, then we need to know wheather the youngest non-squashed microop was marked delayed commit or not. I don't know if it possible to figure out the youngest non-squashed microop from the fetch stage. Setting the flag to true will at least ensure that the interrupts are not handled when they cannot be, though we may also miss out on some opportunities to handle interrupts. - Nilay ----------------------------------------------------------- This is an automatically generated e-mail. To reply, visit: http://reviews.gem5.org/r/1019/#review2047 ----------------------------------------------------------- On Jan. 28, 2012, 9:02 p.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1019/ > ----------------------------------------------------------- > > (Updated Jan. 28, 2012, 9:02 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8733:46a19d5999bd > --------------------------- > O3 CPU: Improve handling of delayed commit flag > The delayed commit flag is used in conjunction with interrupt pending flag to > figure out whether or not fetch stage should get more instructions. This patch > clears this flag when instructions are squashed. Also, in case an interrupt is > pending, currently it is not possible to access the instruction cache. This > patch allows accessing the cache in case this flag is set. > > > Diffs > ----- > > src/cpu/o3/fetch_impl.hh 9d7c1dc54954 > > Diff: http://reviews.gem5.org/r/1019/diff/diff > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
