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src/arch/alpha/tlb.cc <http://reviews.gem5.org/r/1032/#comment2600> If these don't do anything and the caller won't expect/handle that, they should panic and say they're not implemented. src/cpu/checker/cpu_impl.hh <http://reviews.gem5.org/r/1032/#comment2602> What's this from? I won't say it's not somewhere else or that it shouldn't be here, but I don't remember it. Also, the preprocessor is supposed to require #s to be all the way to the left. src/cpu/checker/cpu_impl.hh <http://reviews.gem5.org/r/1032/#comment2603> You're checking for x86 here too. It's normally equivalent and generally harmless to compare ExtMachInsts instead of MachInsts. The difference is that the ExtMachInsts have been contextualized and the MachInsts are just the raw bytes from memory. In the x86 case exactly what should be the MachInst is ambiguous, but not the ExtMachInst. src/cpu/o3/iew_impl.hh <http://reviews.gem5.org/r/1032/#comment2604> This looks pretty strange. Was this dead code? Did you bring it back to life here on purpose? Or in other words, is reintroducing it the right thing to do, or is it obsolete code? - Gabe Black On Feb. 8, 2012, 7:46 a.m., Geoffrey Blake wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1032/ > ----------------------------------------------------------- > > (Updated Feb. 8, 2012, 7:46 a.m.) > > > Review request for Default. > > > Description > ------- > > CheckerCPU: Add function stubs to non-ARM ISA source to compile with > CheckerCPU > > Making the CheckerCPU a runtime time option requires the code to be compatible > with ISAs other than ARM. This patch adds the appropriate function > stubs to allow compilation. > > > Diffs > ----- > > src/arch/alpha/tlb.hh 8f354c5a1634 > src/arch/alpha/tlb.cc 8f354c5a1634 > src/arch/mips/tlb.hh 8f354c5a1634 > src/arch/mips/tlb.cc 8f354c5a1634 > src/arch/power/tlb.hh 8f354c5a1634 > src/arch/power/tlb.cc 8f354c5a1634 > src/arch/sparc/tlb.hh 8f354c5a1634 > src/arch/sparc/tlb.cc 8f354c5a1634 > src/arch/x86/tlb.hh 8f354c5a1634 > src/arch/x86/tlb.cc 8f354c5a1634 > src/cpu/checker/cpu.hh 8f354c5a1634 > src/cpu/checker/cpu_impl.hh 8f354c5a1634 > src/cpu/inorder/thread_context.hh 8f354c5a1634 > src/cpu/o3/commit_impl.hh 8f354c5a1634 > src/cpu/o3/iew_impl.hh 8f354c5a1634 > src/cpu/ozone/back_end_impl.hh 8f354c5a1634 > src/cpu/ozone/lw_back_end_impl.hh 8f354c5a1634 > > Diff: http://reviews.gem5.org/r/1032/diff/diff > > > Testing > ------- > > Compiles for all ISAs. > > > Thanks, > > Geoffrey Blake > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
