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(Updated Feb. 9, 2012, 11:45 a.m.) Review request for Default. Description (updated) ------- MEM: Introduce the master/slave port roles in the Python classes This patch classifies all ports in Python as either Master or Slave and enforces a binding of master to slave. Conceptually, a master (such as a CPU or DMA port) issues requests, and receives responses, and conversely, a slave (such as a memory or a PIO device) receives requests and sends back responses. Currently there is no differentiation between coherent and non-coherent masters and slaves. The classification as master/slave also involves splitting the dual role port of the bus into a master and slave port and updating all the system assembly scripts to use the appropriate port. Similarly, the interrupt devices have to have their int_port split into a master and slave port. The intdev and its children have minimal changes to facilitate the extra port. Note that this patch does not enforce any port typing in the C++ world, it merely ensures that the Python objects have a notion of the port roles and are connected in an appropriate manner. This check is carried when two ports are connected, e.g. bus.master = memory.port. The following patches will make use of the classifications and specialise the C++ ports into masters and slaves. Diffs (updated) ----- configs/common/CacheConfig.py 4f2ad221ae32 configs/common/FSConfig.py 4f2ad221ae32 configs/example/fs.py 4f2ad221ae32 configs/example/ruby_fs.py 4f2ad221ae32 configs/example/se.py 4f2ad221ae32 configs/ruby/Ruby.py 4f2ad221ae32 src/arch/arm/ArmTLB.py 4f2ad221ae32 src/arch/x86/X86LocalApic.py 4f2ad221ae32 src/arch/x86/X86TLB.py 4f2ad221ae32 src/arch/x86/interrupts.hh 4f2ad221ae32 src/cpu/BaseCPU.py 4f2ad221ae32 src/cpu/simple/AtomicSimpleCPU.py 4f2ad221ae32 src/cpu/testers/directedtest/RubyDirectedTester.py 4f2ad221ae32 src/cpu/testers/memtest/MemTest.py 4f2ad221ae32 src/cpu/testers/networktest/NetworkTest.py 4f2ad221ae32 src/cpu/testers/rubytest/RubyTester.py 4f2ad221ae32 src/dev/Device.py 4f2ad221ae32 src/dev/Ethernet.py 4f2ad221ae32 src/dev/Pci.py 4f2ad221ae32 src/dev/alpha/Tsunami.py 4f2ad221ae32 src/dev/arm/RealView.py 4f2ad221ae32 src/dev/x86/I82094AA.py 4f2ad221ae32 src/dev/x86/Pc.py 4f2ad221ae32 src/dev/x86/SouthBridge.py 4f2ad221ae32 src/dev/x86/i82094aa.hh 4f2ad221ae32 src/dev/x86/intdev.hh 4f2ad221ae32 src/mem/Bridge.py 4f2ad221ae32 src/mem/Bus.py 4f2ad221ae32 src/mem/PhysicalMemory.py 4f2ad221ae32 src/mem/cache/BaseCache.py 4f2ad221ae32 src/mem/ruby/system/RubyPort.cc 4f2ad221ae32 src/mem/ruby/system/Sequencer.py 4f2ad221ae32 src/python/m5/params.py 4f2ad221ae32 src/sim/System.py 4f2ad221ae32 tests/configs/inorder-timing.py 4f2ad221ae32 tests/configs/memtest-ruby.py 4f2ad221ae32 tests/configs/memtest.py 4f2ad221ae32 tests/configs/o3-timing-mp-ruby.py 4f2ad221ae32 tests/configs/o3-timing-mp.py 4f2ad221ae32 tests/configs/o3-timing-ruby.py 4f2ad221ae32 tests/configs/o3-timing.py 4f2ad221ae32 tests/configs/pc-o3-timing.py 4f2ad221ae32 tests/configs/pc-simple-atomic.py 4f2ad221ae32 tests/configs/pc-simple-timing.py 4f2ad221ae32 tests/configs/realview-o3-dual.py 4f2ad221ae32 tests/configs/realview-o3.py 4f2ad221ae32 tests/configs/realview-simple-atomic-dual.py 4f2ad221ae32 tests/configs/realview-simple-atomic.py 4f2ad221ae32 tests/configs/realview-simple-timing-dual.py 4f2ad221ae32 tests/configs/realview-simple-timing.py 4f2ad221ae32 tests/configs/rubytest-ruby.py 4f2ad221ae32 tests/configs/simple-atomic-mp-ruby.py 4f2ad221ae32 tests/configs/simple-atomic-mp.py 4f2ad221ae32 tests/configs/simple-atomic.py 4f2ad221ae32 tests/configs/simple-timing-mp.py 4f2ad221ae32 tests/configs/simple-timing.py 4f2ad221ae32 tests/configs/tsunami-inorder.py 4f2ad221ae32 tests/configs/tsunami-o3-dual.py 4f2ad221ae32 tests/configs/tsunami-o3.py 4f2ad221ae32 tests/configs/tsunami-simple-atomic-dual.py 4f2ad221ae32 tests/configs/tsunami-simple-atomic.py 4f2ad221ae32 tests/configs/tsunami-simple-timing-dual.py 4f2ad221ae32 tests/configs/tsunami-simple-timing.py 4f2ad221ae32 tests/configs/twosys-tsunami-simple-atomic.py 4f2ad221ae32 Diff: http://reviews.gem5.org/r/1001/diff/diff Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
