changeset e7ae13867098 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=e7ae13867098
description:
O3 CPU: Provide the squashing instruction
This patch adds a function to the ROB that will get the squashing
instruction
from the ROB's list of instructions. This squashing instruction is used
for
figuring out the macroop from which the fetch stage should fetch the
microops.
Further, a check has been added that if the instructions are to be
fetched
from the cache maintained by the fetch stage, then the data in the
cache should
be valid and the PC of the thread being fetched from is same as the
address of
the cache block.
diffstat:
src/cpu/o3/commit_impl.hh | 3 ++-
src/cpu/o3/fetch_impl.hh | 7 +++++++
src/cpu/o3/rob.hh | 5 +++++
src/cpu/o3/rob_impl.hh | 11 +++++++++++
4 files changed, 25 insertions(+), 1 deletions(-)
diffs (65 lines):
diff -r bba1a976c293 -r e7ae13867098 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh Fri Feb 10 08:37:26 2012 -0600
+++ b/src/cpu/o3/commit_impl.hh Fri Feb 10 08:37:28 2012 -0600
@@ -856,7 +856,8 @@
fromIEW->mispredictInst[tid];
toIEW->commitInfo[tid].branchTaken =
fromIEW->branchTaken[tid];
- toIEW->commitInfo[tid].squashInst = NULL;
+ toIEW->commitInfo[tid].squashInst =
+ rob->findInst(tid, squashed_inst);
toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
diff -r bba1a976c293 -r e7ae13867098 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Fri Feb 10 08:37:26 2012 -0600
+++ b/src/cpu/o3/fetch_impl.hh Fri Feb 10 08:37:28 2012 -0600
@@ -1189,8 +1189,15 @@
// StaticInst from the rom, the current macroop, or what's already
// in the predecoder.
bool needMem = !inRom && !curMacroop && !predecoder.extMachInstReady();
+ fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
+ Addr block_PC = icacheBlockAlignPC(fetchAddr);
if (needMem) {
+ // If buffer is no longer valid or fetchAddr has moved to point
+ // to the next cache block then start fetch from icache.
+ if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid])
+ break;
+
if (blkOffset >= numInsts) {
// We need to process more memory, but we've run out of the
// current block.
diff -r bba1a976c293 -r e7ae13867098 src/cpu/o3/rob.hh
--- a/src/cpu/o3/rob.hh Fri Feb 10 08:37:26 2012 -0600
+++ b/src/cpu/o3/rob.hh Fri Feb 10 08:37:28 2012 -0600
@@ -122,6 +122,11 @@
*/
DynInstPtr readHeadInst(ThreadID tid);
+ /** Returns a pointer to the instruction with the given sequence if it is
+ * in the ROB.
+ */
+ DynInstPtr findInst(ThreadID tid, InstSeqNum squash_inst);
+
/** Returns pointer to the tail instruction within the ROB. There is
* no guarantee as to the return value if the ROB is empty.
* @retval Pointer to the DynInst that is at the tail of the ROB.
diff -r bba1a976c293 -r e7ae13867098 src/cpu/o3/rob_impl.hh
--- a/src/cpu/o3/rob_impl.hh Fri Feb 10 08:37:26 2012 -0600
+++ b/src/cpu/o3/rob_impl.hh Fri Feb 10 08:37:28 2012 -0600
@@ -544,3 +544,14 @@
.desc("The number of ROB writes");
}
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::findInst(ThreadID tid, InstSeqNum squash_inst)
+{
+ for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++) {
+ if ((*it)->seqNum == squash_inst) {
+ return *it;
+ }
+ }
+ return NULL;
+}
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