changeset a451e4eda591 in /z/repo/gem5 details: http://repo.gem5.org/gem5?cmd=changeset;node=a451e4eda591 description: bp: fix up stats for changes to branch predictor
diffstat: tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout | 8 +- tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt | 2752 +++--- tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout | 6 +- tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt | 1351 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout | 6 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 2708 +++--- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout | 6 +- tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1417 ++-- tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout | 6 +- tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt | 1558 ++-- tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout | 6 +- tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt | 534 +- tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt | 1024 +- tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt | 1067 +- tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout | 6 +- tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt | 1004 +- tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout | 8 +- tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt | 974 +- tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt | 1066 +- tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout | 8 +- tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt | 978 +- tests/long/se/20.parser/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt | 1112 +- tests/long/se/20.parser/ref/x86/linux/o3-timing/simout | 23 +- tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt | 1017 +- tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout | 6 +- tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt | 454 +- tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout | 8 +- tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt | 1048 +- tests/long/se/30.eon/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt | 1014 +- tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt | 1030 +- tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt | 1075 +- tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout | 6 +- tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt | 594 +- tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt | 1048 +- tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt | 1111 +- tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout | 6 +- tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt | 508 +- tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout | 6 +- tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt | 1030 +- tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout | 6 +- tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt | 1076 +- tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout | 8 +- tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt | 490 +- tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout | 8 +- tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt | 1012 +- tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout | 8 +- tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt | 1055 +- tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout | 8 +- tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt | 964 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini | 98 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr | 29 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout | 9 +- tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt | 571 + tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout | 6 +- tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt | 326 +- tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout | 6 +- tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt | 896 +- tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout | 6 +- tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt | 855 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout | 6 +- tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt | 897 +- tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout | 6 +- tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt | 298 +- tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout | 6 +- tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt | 820 +- tests/quick/se/00.hello/ref/power/linux/o3-timing/simout | 6 +- tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt | 905 +- tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout | 6 +- tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt | 274 +- tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout | 6 +- tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt | 834 +- tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout | 6 +- tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt | 1095 +- tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout | 6 +- tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt | 280 +- tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout | 6 +- tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt | 802 +- tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout | 56 +- tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt | 3519 ++++----- 88 files changed, 22752 insertions(+), 22162 deletions(-) diffs (truncated from 51090 to 300 lines): diff -r 7d3ac6813147 -r a451e4eda591 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Feb 13 12:26:25 2012 -0600 +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Feb 13 12:30:30 2012 -0600 @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 11 2012 13:05:17 -gem5 started Feb 11 2012 13:47:49 +gem5 compiled Feb 12 2012 17:15:14 +gem5 started Feb 12 2012 18:11:03 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -info: Launching CPU 1 @ 106949500 -Exiting @ tick 1897464893500 because m5_exit instruction encountered +info: Launching CPU 1 @ 107002000 +Exiting @ tick 1899401490000 because m5_exit instruction encountered diff -r 7d3ac6813147 -r a451e4eda591 tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt --- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Mon Feb 13 12:26:25 2012 -0600 +++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Mon Feb 13 12:30:30 2012 -0600 @@ -1,179 +1,179 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.897465 # Number of seconds simulated -sim_ticks 1897464893500 # Number of ticks simulated -final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.899401 # Number of seconds simulated +sim_ticks 1899401490000 # Number of ticks simulated +final_tick 1899401490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 189830 # Simulator instruction rate (inst/s) -host_op_rate 189830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6418636186 # Simulator tick rate (ticks/s) -host_mem_usage 296280 # Number of bytes of host memory used -host_seconds 295.62 # Real time elapsed on the host -sim_insts 56117221 # Number of instructions simulated -sim_ops 56117221 # Number of ops (including micro ops) simulated -system.physmem.bytes_read 30408512 # Number of bytes read from this memory -system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory -system.physmem.bytes_written 10470144 # Number of bytes written to this memory -system.physmem.num_reads 475133 # Number of read requests responded to by this memory -system.physmem.num_writes 163596 # Number of write requests responded to by this memory +host_inst_rate 189434 # Simulator instruction rate (inst/s) +host_op_rate 189434 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6363739723 # Simulator tick rate (ticks/s) +host_mem_usage 296196 # Number of bytes of host memory used +host_seconds 298.47 # Real time elapsed on the host +sim_insts 56540749 # Number of instructions simulated +sim_ops 56540749 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 30421696 # Number of bytes read from this memory +system.physmem.bytes_inst_read 1133376 # Number of instructions bytes read from this memory +system.physmem.bytes_written 10508736 # Number of bytes written to this memory +system.physmem.num_reads 475339 # Number of read requests responded to by this memory +system.physmem.num_writes 164199 # Number of write requests responded to by this memory system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 16025863 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read 579367 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write 5517965 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 21543827 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 397850 # number of replacements -system.l2c.tagsinuse 35109.782430 # Cycle average of tags in use -system.l2c.total_refs 2482376 # Total number of references to valid blocks. -system.l2c.sampled_refs 433566 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.725486 # Average number of references to valid blocks. -system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 126.484558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.062074 # 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number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 27 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 168180 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 11095 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 955732 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 932654 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 109195 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 49204 # number of demand (read+write) hits -system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 955732 # number of overall hits -system.l2c.overall_hits::cpu0.data 932654 # number of overall hits -system.l2c.overall_hits::cpu1.inst 109195 # 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miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.017633 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.206848 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015690 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.302369 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.017633 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.206848 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52307.371669 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52034.407224 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52320.408163 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 53022.291467 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1007.355946 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2880.782918 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 9333.333333 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 2494.047619 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52459.499684 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52456.169738 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52307.371669 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 52154.171841 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 52320.408163 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52307.371669 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 52154.171841 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 52320.408163 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52548.199813 # average overall miss latency +system.physmem.bw_read 16016464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 596702 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 5532657 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 21549121 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 397771 # number of replacements +system.l2c.tagsinuse 35743.917451 # Cycle average of tags in use +system.l2c.total_refs 2469954 # Total number of references to valid blocks. +system.l2c.sampled_refs 433727 # Sample count of references to valid blocks. +system.l2c.avg_refs 5.694720 # Average number of references to valid blocks. +system.l2c.warmup_cycle 9252138000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 22965.517435 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 2876.895593 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 7557.549613 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1417.164346 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 926.790463 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.350426 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.043898 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.115319 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.021624 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.014142 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.545409 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 910711 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 668584 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 173581 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 117817 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1870693 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 806294 # number of Writeback hits +system.l2c.Writeback_hits::total 806294 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 169 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 126 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 295 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 38 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 32 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 70 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 154146 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 17714 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 171860 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.inst 910711 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 822730 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 173581 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 135531 # number of demand (read+write) hits +system.l2c.demand_hits::total 2042553 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 910711 # number of overall hits +system.l2c.overall_hits::cpu0.data 822730 # number of overall hits +system.l2c.overall_hits::cpu1.inst 173581 # number of overall hits +system.l2c.overall_hits::cpu1.data 135531 # number of overall hits +system.l2c.overall_hits::total 2042553 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 13521 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 288493 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 4207 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 3184 # number of ReadReq misses +system.l2c.ReadReq_misses::total 309405 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 2939 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 698 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 3637 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 248 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 292 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 540 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 109252 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 15963 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 125215 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.inst 13521 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 397745 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4207 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 19147 # number of demand (read+write) misses +system.l2c.demand_misses::total 434620 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 13521 # number of overall misses +system.l2c.overall_misses::cpu0.data 397745 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4207 # number of overall misses +system.l2c.overall_misses::cpu1.data 19147 # number of overall misses +system.l2c.overall_misses::total 434620 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 707237500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 15013277500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 220139500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 161535500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 16102190000 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 2036500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 2558500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 4595000 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4304500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1626000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 5930500 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5731732500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 836680000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6568412500 # number of ReadExReq miss cycles _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
