changeset a230379caf65 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a230379caf65
description:
MEM: Fix master/slave ports in Ruby and non-regression scripts
This patch brings the Ruby and other scripts up to date with the
introduction of the master/slave ports.
diffstat:
configs/example/fs.py | 4 ++--
configs/example/ruby_direct_test.py | 2 +-
configs/example/ruby_fs.py | 8 ++++----
configs/example/ruby_mem_test.py | 2 +-
configs/example/ruby_network_test.py | 2 +-
configs/example/ruby_random_test.py | 2 +-
configs/example/se.py | 4 ++--
configs/ruby/MESI_CMP_directory.py | 6 +++---
configs/ruby/MI_example.py | 8 ++++----
configs/ruby/MOESI_CMP_directory.py | 6 +++---
configs/ruby/MOESI_CMP_token.py | 6 +++---
configs/ruby/MOESI_hammer.py | 6 +++---
configs/ruby/Network_test.py | 2 +-
13 files changed, 29 insertions(+), 29 deletions(-)
diffs (229 lines):
diff -r a451e4eda591 -r a230379caf65 configs/example/fs.py
--- a/configs/example/fs.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/fs.py Tue Feb 14 03:41:53 2012 -0500
@@ -195,8 +195,8 @@
drive_sys.kernel = binary(options.kernel)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(bm[1].mem())])
- drive_sys.iobridge.slave = drive_sys.iobus.port
- drive_sys.iobridge.master = drive_sys.membus.port
+ drive_sys.iobridge.slave = drive_sys.iobus.master
+ drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.init_param = options.init_param
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
diff -r a451e4eda591 -r a230379caf65 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_direct_test.py Tue Feb 14 03:41:53 2012 -0500
@@ -102,7 +102,7 @@
#
# Tie the ruby tester ports to the ruby cpu ports
#
- system.tester.cpuPort = ruby_port.port
+ system.tester.cpuPort = ruby_port.slave
# -----------------------
# run simulation
diff -r a451e4eda591 -r a230379caf65 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_fs.py Tue Feb 14 03:41:53 2012 -0500
@@ -125,11 +125,11 @@
#
# Tie the cpu ports to the correct ruby system ports
#
- cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
+ cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
- cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
+ cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
+ cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
cpu.interrupts.pio = system.piobus.master
cpu.interrupts.int_master = system.piobus.slave
cpu.interrupts.int_slave = system.piobus.master
diff -r a451e4eda591 -r a230379caf65 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_mem_test.py Tue Feb 14 03:41:53 2012 -0500
@@ -133,7 +133,7 @@
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby._cpu_ruby_ports[i].port
+ cpu.test = system.ruby._cpu_ruby_ports[i].slave
cpu.functional = system.funcmem.port
#
diff -r a451e4eda591 -r a230379caf65 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_network_test.py Tue Feb 14 03:41:53 2012 -0500
@@ -109,7 +109,7 @@
#
# Tie the cpu test ports to the ruby cpu port
#
- cpus[i].test = ruby_port.port
+ cpus[i].test = ruby_port.slave
ruby_port.access_phys_mem = False
i += 1
diff -r a451e4eda591 -r a230379caf65 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_random_test.py Tue Feb 14 03:41:53 2012 -0500
@@ -110,7 +110,7 @@
#
# Tie the ruby tester ports to the ruby cpu ports
#
- tester.cpuPort = ruby_port.port
+ tester.cpuPort = ruby_port.slave
#
# Tell each sequencer this is the ruby tester so that it
diff -r a451e4eda591 -r a230379caf65 configs/example/se.py
--- a/configs/example/se.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/se.py Tue Feb 14 03:41:53 2012 -0500
@@ -190,8 +190,8 @@
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
- system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
- system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
+ system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
+ system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
diff -r a451e4eda591 -r a230379caf65 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MESI_CMP_directory.py Tue Feb 14 03:41:53 2012 -0500
@@ -103,7 +103,7 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
@@ -180,9 +180,9 @@
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" %
i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff -r a451e4eda591 -r a230379caf65 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MI_example.py Tue Feb 14 03:41:53 2012 -0500
@@ -95,7 +95,7 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -153,10 +153,10 @@
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" %
i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
- dma_cntrl.dma_sequencer.port = dma_device.dma
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
+ dma_cntrl.dma_sequencer.slave = dma_device.dma
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff -r a451e4eda591 -r a230379caf65 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MOESI_CMP_directory.py Tue Feb 14 03:41:53 2012 -0500
@@ -103,7 +103,7 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -177,9 +177,9 @@
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" %
i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff -r a451e4eda591 -r a230379caf65 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MOESI_CMP_token.py Tue Feb 14 03:41:53 2012 -0500
@@ -125,7 +125,7 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
@@ -201,9 +201,9 @@
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" %
i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
cntrl_count += 1
diff -r a451e4eda591 -r a230379caf65 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MOESI_hammer.py Tue Feb 14 03:41:53 2012 -0500
@@ -118,7 +118,7 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
@@ -213,9 +213,9 @@
exec("system.dma_cntrl%d = dma_cntrl" % i)
if dma_device.type == 'MemTest':
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" %
i)
else:
- exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+ exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
dma_cntrl_nodes.append(dma_cntrl)
if options.recycle_latency:
diff -r a451e4eda591 -r a230379caf65 configs/ruby/Network_test.py
--- a/configs/ruby/Network_test.py Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/Network_test.py Tue Feb 14 03:41:53 2012 -0500
@@ -96,7 +96,7 @@
l1_cntrl.sequencer = cpu_seq
if piobus != None:
- cpu_seq.pio_port = piobus.port
+ cpu_seq.pio_port = piobus.slave
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
