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Ship it! Looks fine, comments below are minor/optional. src/cpu/testers/directedtest/RubyDirectedTester.cc <http://reviews.gem5.org/r/1047/#comment2678> Is this cast really necessary? Looks like ports.size() should be a size_t. I'm curious what error/warning we get if we leave it out... src/mem/bus.cc <http://reviews.gem5.org/r/1047/#comment2679> Does it make more sense to just maintain two separate vectors, one for masters and one for slaves? It'd require more extensive changes to the rest of the bus code, but it might actually clean it up a bit... maybe you're already doing this in some future patch I haven't seen yet. - Steve Reinhardt On Feb. 14, 2012, 10:41 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1047/ > ----------------------------------------------------------- > > (Updated Feb. 14, 2012, 10:41 a.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Move port creation to the memory object(s) construction > > This patch moves all port creation from the getPort method to be > consistently done in the MemObject's constructor. This is possible > thanks to the Swig interface passing the length of the vector ports. > Previously there was a mix of: 1) creating the ports as members (at > object construction time) and using getPort for the name resolution, > or 2) dynamically creating the ports in the getPort call. This is now > uniform. Furthermore, objects that would not be complete without a > port have these ports as members rather than having pointers to > dynamically allocated ports. > > This patch also enables an elaboration-time enumeration of all the > ports in the system which can be used to determine the masterId. > > > Diffs > ----- > > src/arch/arm/table_walker.hh 2eaf1809c6c6 > src/arch/arm/table_walker.cc 2eaf1809c6c6 > src/arch/x86/interrupts.hh 2eaf1809c6c6 > src/arch/x86/interrupts.cc 2eaf1809c6c6 > src/cpu/testers/directedtest/RubyDirectedTester.cc 2eaf1809c6c6 > src/cpu/testers/rubytest/RubyTester.cc 2eaf1809c6c6 > src/dev/alpha/tsunami_pchip.cc 2eaf1809c6c6 > src/dev/arm/pl111.cc 2eaf1809c6c6 > src/dev/copy_engine.hh 2eaf1809c6c6 > src/dev/copy_engine.cc 2eaf1809c6c6 > src/dev/i8254xGBe.cc 2eaf1809c6c6 > src/dev/io_device.hh 2eaf1809c6c6 > src/dev/io_device.cc 2eaf1809c6c6 > src/dev/mips/malta_pchip.cc 2eaf1809c6c6 > src/dev/pcidev.hh 2eaf1809c6c6 > src/dev/pcidev.cc 2eaf1809c6c6 > src/dev/sinic.cc 2eaf1809c6c6 > src/dev/x86/i82094aa.hh 2eaf1809c6c6 > src/dev/x86/i82094aa.cc 2eaf1809c6c6 > src/dev/x86/intdev.hh 2eaf1809c6c6 > src/dev/x86/intdev.cc 2eaf1809c6c6 > src/mem/bridge.hh 2eaf1809c6c6 > src/mem/bridge.cc 2eaf1809c6c6 > src/mem/bus.hh 2eaf1809c6c6 > src/mem/bus.cc 2eaf1809c6c6 > src/mem/physical.cc 2eaf1809c6c6 > src/mem/ruby/system/RubyPort.hh 2eaf1809c6c6 > src/mem/ruby/system/RubyPort.cc 2eaf1809c6c6 > > Diff: http://reviews.gem5.org/r/1047/diff/diff > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
