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I'd like to see a check in cpu/base.cc to ensure that the interrupts are really set properly. Currently it seems that failing to call createInterrupts would result in a segfault. - Andreas Hansson On Feb. 28, 2012, 6:41 a.m., Nilay Vaish wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1066/ > ----------------------------------------------------------- > > (Updated Feb. 28, 2012, 6:41 a.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 8859:7e91ef576149 > --------------------------- > Fix switching of CPUs > This patch prevents creation of interrupt controller for > cpus that will be switched in later > > > Diffs > ----- > > configs/common/CacheConfig.py c68ae0f78d8e > configs/example/fs.py c68ae0f78d8e > src/cpu/BaseCPU.py c68ae0f78d8e > src/cpu/o3/cpu.cc c68ae0f78d8e > > Diff: http://reviews.gem5.org/r/1066/diff/ > > > Testing > ------- > > > Thanks, > > Nilay Vaish > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
