changeset 26dbd171754e in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=26dbd171754e
description:
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
diffstat:
src/arch/arm/isa.cc | 21 +++++++---
src/arch/arm/isa/decoder/arm.isa | 3 +-
src/arch/arm/isa/decoder/thumb.isa | 4 +-
src/arch/arm/isa/formats/misc.isa | 45 ++++++++++++++++++++++-
src/arch/arm/isa/formats/uncond.isa | 4 +-
src/arch/arm/isa/insts/misc.isa | 54 ++++++++++++++++++++++++++-
src/arch/arm/miscregs.cc | 32 +++++++++++++++-
src/arch/arm/miscregs.hh | 73 ++++++++++++++++++++++++++++++++++++-
8 files changed, 223 insertions(+), 13 deletions(-)
diffs (truncated from 382 to 300 lines):
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/isa.cc Thu Mar 01 17:26:31 2012 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2011 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -233,11 +233,20 @@
case MISCREG_FPSCR_EXC:
return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
case MISCREG_L2CTLR:
- // mostly unimplemented, just set NumCPUs field from sim and return
- L2CTLR l2ctlr = 0;
- // b00:1CPU to b11:4CPUs
- l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
- return l2ctlr;
+ {
+ // mostly unimplemented, just set NumCPUs field from sim and return
+ L2CTLR l2ctlr = 0;
+ // b00:1CPU to b11:4CPUs
+ l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
+ return l2ctlr;
+ }
+ case MISCREG_DBGDIDR:
+ /* For now just implement the version number.
+ * Return 0 as we don't support debug architecture yet.
+ */
+ return 0;
+ case MISCREG_DBGDSCR_INT:
+ return 0;
}
return readMiscRegNoEffect(misc_reg);
}
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/isa/decoder/arm.isa
--- a/src/arch/arm/isa/decoder/arm.isa Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/isa/decoder/arm.isa Thu Mar 01 17:26:31 2012 -0600
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -114,6 +114,7 @@
1: decode CPNUM { // 27-24=1110,4 ==1
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
+ 0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
} // CPNUM (OP4 == 1)
} //OPCODE_4
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/isa/decoder/thumb.isa
--- a/src/arch/arm/isa/decoder/thumb.isa Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/isa/decoder/thumb.isa Thu Mar 01 17:26:31 2012 -0600
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -86,6 +86,7 @@
0x1: decode LTCOPROC {
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
+ 0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
}
}
@@ -142,6 +143,7 @@
0x1: decode LTCOPROC {
0x1: M5ops::m5ops();
0xa, 0xb: ShortFpTransfer::shortFpTransfer();
+ 0xe: McrMrc14::mcrMrc14();
0xf: McrMrc15::mcrMrc15();
}
}
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/isa/formats/misc.isa
--- a/src/arch/arm/isa/formats/misc.isa Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/isa/formats/misc.isa Thu Mar 01 17:26:31 2012 -0600
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -85,6 +85,49 @@
'''
decoder_output = '''
StaticInstPtr
+ decodeMcrMrc14(ExtMachInst machInst)
+ {
+ const uint32_t opc1 = bits(machInst, 23, 21);
+ const uint32_t crn = bits(machInst, 19, 16);
+ const uint32_t opc2 = bits(machInst, 7, 5);
+ const uint32_t crm = bits(machInst, 3, 0);
+ const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
+ const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+
+ const bool isRead = bits(machInst, 20);
+
+ switch (miscReg) {
+ case MISCREG_NOP:
+ return new NopInst(machInst);
+ case NUM_MISCREGS:
+ return new FailUnimplemented(
+ csprintf("miscreg crn:%d opc1:%d crm:%d opc2:%d %s
unknown",
+ crn, opc1, crm, opc2, isRead ? "read" : "write").c_str(),
+ machInst);
+ default:
+ if (isRead) {
+ return new Mrc14(machInst, rt, (IntRegIndex)miscReg);
+ } else {
+ return new Mcr14(machInst, (IntRegIndex)miscReg, rt);
+ }
+ }
+ }
+ '''
+}};
+
+def format McrMrc14() {{
+ decode_block = '''
+ return decodeMcrMrc14(machInst);
+ '''
+}};
+
+let {{
+ header_output = '''
+ StaticInstPtr
+ decodeMcrMrc15(ExtMachInst machInst);
+ '''
+ decoder_output = '''
+ StaticInstPtr
decodeMcrMrc15(ExtMachInst machInst)
{
const uint32_t opc1 = bits(machInst, 23, 21);
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/isa/formats/uncond.isa
--- a/src/arch/arm/isa/formats/uncond.isa Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/isa/formats/uncond.isa Thu Mar 01 17:26:31 2012 -0600
@@ -1,4 +1,4 @@
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -269,6 +269,8 @@
if (bits(op1, 4) == 0) {
if (CPNUM == 0xa || CPNUM == 0xb) {
return decodeShortFpTransfer(machInst);
+ } else if (CPNUM == 0xe) {
+ return decodeMcrMrc14(machInst);
} else if (CPNUM == 0xf) {
return decodeMcrMrc15(machInst);
}
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/isa/insts/misc.isa Thu Mar 01 17:26:31 2012 -0600
@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
-// Copyright (c) 2010 ARM Limited
+// Copyright (c) 2010-2012 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -626,6 +626,58 @@
decoder_output += RegRegImmImmOpConstructor.subst(bfiIop)
exec_output += PredOpExecute.subst(bfiIop)
+ mrc14code = '''
+ CPSR cpsr = Cpsr;
+ if (cpsr.mode == MODE_USER) {
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
+ }
+ Dest = MiscOp1;
+ '''
+
+ mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegOp",
+ { "code": mrc14code,
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegOpDeclare.subst(mrc14Iop)
+ decoder_output += RegRegOpConstructor.subst(mrc14Iop)
+ exec_output += PredOpExecute.subst(mrc14Iop)
+
+
+ mcr14code = '''
+ CPSR cpsr = Cpsr;
+ if (cpsr.mode == MODE_USER) {
+ if (FullSystem)
+ return new UndefinedInstruction;
+ else
+ return new UndefinedInstruction(false, mnemonic);
+ }
+ MiscDest = Op1;
+ '''
+ mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegOp",
+ { "code": mcr14code,
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
+ header_output += RegRegOpDeclare.subst(mcr14Iop)
+ decoder_output += RegRegOpConstructor.subst(mcr14Iop)
+ exec_output += PredOpExecute.subst(mcr14Iop)
+
+ mrc14UserIop = InstObjParams("mrc", "Mrc14User", "RegRegOp",
+ { "code": "Dest = MiscOp1;",
+ "predicate_test": predicateTest }, [])
+ header_output += RegRegOpDeclare.subst(mrc14UserIop)
+ decoder_output += RegRegOpConstructor.subst(mrc14UserIop)
+ exec_output += PredOpExecute.subst(mrc14UserIop)
+
+ mcr14UserIop = InstObjParams("mcr", "Mcr14User", "RegRegOp",
+ { "code": "MiscDest = Op1",
+ "predicate_test": predicateTest },
+ ["IsSerializeAfter","IsNonSpeculative"])
+ header_output += RegRegOpDeclare.subst(mcr14UserIop)
+ decoder_output += RegRegOpConstructor.subst(mcr14UserIop)
+ exec_output += PredOpExecute.subst(mcr14UserIop)
+
mrc15code = '''
CPSR cpsr = Cpsr;
if (cpsr.mode == MODE_USER) {
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/miscregs.cc Thu Mar 01 17:26:31 2012 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -46,6 +46,36 @@
{
MiscRegIndex
+decodeCP14Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
+{
+ switch(crn) {
+ case 0:
+ switch (opc2) {
+ case 0:
+ switch (crm) {
+ case 0:
+ return MISCREG_DBGDIDR;
+ case 1:
+ return MISCREG_DBGDSCR_INT;
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+ default:
+ warn("CP14 unimplemented crn[%d], opc1[%d], crm[%d], opc2[%d]",
+ crn, opc1, crm, opc2);
+ return NUM_MISCREGS;
+ }
+
+}
+
+MiscRegIndex
decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
{
switch (crn) {
diff -r 08cc303b718b -r 26dbd171754e src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Thu Mar 01 17:26:31 2012 -0600
+++ b/src/arch/arm/miscregs.hh Thu Mar 01 17:26:31 2012 -0600
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -86,6 +86,41 @@
MISCREG_SCTLR_RST,
MISCREG_SEV_MAILBOX,
+ // CP14 registers
+ MISCREG_CP14_START,
+ MISCREG_DBGDIDR = MISCREG_CP14_START,
+ MISCREG_DBGDSCR_INT,
+ MISCREG_DBGDTRRX_INT,
+ MISCREG_DBGTRTX_INT,
+ MISCREG_DBGWFAR,
+ MISCREG_DBGVCR,
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