Hi Pritha, Could you post this to review board. See the section talking about post review on: http://gem5.org/Commit_Access
Thanks, Ali On Mar 3, 2012, at 12:45 PM, Pritha Ghoshal wrote: > # HG changeset patch > # User Pritha Ghoshal <[email protected]> > # Date 1330799635 21600 > # Node ID 29218340fa692ae117aecdbe62ff044ad6b010b9 > # Parent 2629f0b99e8d78f67a3f731d3db3e389aac847c9 > Modifying writeback conditions for i8254xgbe for updated datasheet > > diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc > --- a/src/dev/i8254xGBe.cc > +++ b/src/dev/i8254xGBe.cc > @@ -1923,12 +1923,12 @@ > igbe->anBegin("TXS", "Desc Writeback"); > DPRINTF(EthernetDesc, "WTHRESH == 0, writing back descriptor\n"); > writeback(0); > - } else if (igbe->regs.txdctl.gran() && igbe->regs.txdctl.wthresh() >= > + } else if ((igbe->regs.txdctl.gran()==0) && igbe->regs.txdctl.wthresh() > <= > descInBlock(usedCache.size())) { > DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); > igbe->anBegin("TXS", "Desc Writeback"); > writeback((igbe->cacheBlockSize()-1)>>4); > - } else if (igbe->regs.txdctl.wthresh() >= usedCache.size()) { > + } else if (igbe->regs.txdctl.wthresh() <= usedCache.size()) { > DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); > igbe->anBegin("TXS", "Desc Writeback"); > writeback((igbe->cacheBlockSize()-1)>>4); > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
