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Ship it! Ship It! - Steve Reinhardt On March 20, 2012, 10:32 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1108/ > ----------------------------------------------------------- > > (Updated March 20, 2012, 10:32 a.m.) > > > Review request for Default. > > > Description > ------- > > Atomic: Remove the physmem_port and access memory directly > > This patch removes the physmem_port from the Atomic CPU and instead > uses the system pointer to access the physmem when using the fastmem > option. The system already keeps track of the physmem and the valid > memory address ranges, and with this patch we merely make use of that > existing functionality. As a result of this change, the overloaded > getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs. > > > Diffs > ----- > > configs/example/fs.py c739a3a829f5 > configs/example/se.py c739a3a829f5 > src/cpu/base.hh c739a3a829f5 > src/cpu/simple/AtomicSimpleCPU.py c739a3a829f5 > src/cpu/simple/atomic.hh c739a3a829f5 > src/cpu/simple/atomic.cc c739a3a829f5 > > Diff: http://reviews.gem5.org/r/1108/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio), > also running se.py and fs.py with --fastmem > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
