changeset 8c3bd7bea667 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=8c3bd7bea667
description:
MEM: Split SimpleTimingPort into PacketQueue and ports
This patch decouples the queueing and the port interactions to
simplify the introduction of the master and slave ports. By separating
the queueing functionality from the port itself, it becomes much
easier to distinguish between master and slave ports, and still retain
the queueing ability for both (without code duplication).
As part of the split into a PacketQueue and a port, there is now also
a hierarchy of two port classes, QueuedPort and SimpleTimingPort. The
QueuedPort is useful for ports that want to leave the packet
transmission of outgoing packets to the queue and is used by both
master and slave ports. The SimpleTimingPort inherits from the
QueuedPort and adds the implemention of recvTiming and recvFunctional
through recvAtomic.
The PioPort and MessagePort are cleaned up as part of the changes.
diffstat:
src/dev/io_device.cc | 9 +-
src/dev/io_device.hh | 2 +-
src/dev/x86/intdev.cc | 2 +-
src/mem/SConscript | 2 +
src/mem/cache/base.cc | 11 +-
src/mem/cache/base.hh | 35 ++++-
src/mem/cache/cache.hh | 36 +++++-
src/mem/cache/cache_impl.hh | 13 +-
src/mem/mport.hh | 15 +-
src/mem/packet_queue.cc | 205 +++++++++++++++++++++++++++++++++++++
src/mem/packet_queue.hh | 218 ++++++++++++++++++++++++++++++++++++++++
src/mem/physical.cc | 2 +-
src/mem/qport.hh | 101 ++++++++++++++++++
src/mem/ruby/system/RubyPort.cc | 15 +-
src/mem/ruby/system/RubyPort.hh | 10 +-
src/mem/tport.cc | 180 +-------------------------------
src/mem/tport.hh | 160 ++++-------------------------
17 files changed, 650 insertions(+), 366 deletions(-)
diffs (truncated from 1383 to 300 lines):
diff -r 8b223e308b08 -r 8c3bd7bea667 src/dev/io_device.cc
--- a/src/dev/io_device.cc Thu Mar 22 06:34:50 2012 -0400
+++ b/src/dev/io_device.cc Thu Mar 22 06:36:27 2012 -0400
@@ -36,9 +36,10 @@
#include "dev/io_device.hh"
#include "sim/system.hh"
-PioPort::PioPort(PioDevice *dev, System *s, std::string pname)
- : SimpleTimingPort(dev->name() + pname, dev), device(dev)
-{ }
+PioPort::PioPort(PioDevice *dev)
+ : SimpleTimingPort(dev->name() + "-pioport", dev), device(dev)
+{
+}
Tick
@@ -55,7 +56,7 @@
PioDevice::PioDevice(const Params *p)
- : MemObject(p), sys(p->system), pioPort(this, sys)
+ : MemObject(p), sys(p->system), pioPort(this)
{}
PioDevice::~PioDevice()
diff -r 8b223e308b08 -r 8c3bd7bea667 src/dev/io_device.hh
--- a/src/dev/io_device.hh Thu Mar 22 06:34:50 2012 -0400
+++ b/src/dev/io_device.hh Thu Mar 22 06:36:27 2012 -0400
@@ -65,7 +65,7 @@
public:
- PioPort(PioDevice *dev, System *s, std::string pname = "-pioport");
+ PioPort(PioDevice *dev);
};
diff -r 8b223e308b08 -r 8c3bd7bea667 src/dev/x86/intdev.cc
--- a/src/dev/x86/intdev.cc Thu Mar 22 06:34:50 2012 -0400
+++ b/src/dev/x86/intdev.cc Thu Mar 22 06:36:27 2012 -0400
@@ -50,7 +50,7 @@
for (apicIt = apics.begin(); apicIt != apics.end(); apicIt++) {
PacketPtr pkt = buildIntRequest(*apicIt, message);
if (timing) {
- schedSendTiming(pkt, curTick() + latency);
+ queue.schedSendTiming(pkt, curTick() + latency);
// The target handles cleaning up the packet in timing mode.
} else {
// ignore the latency involved in the atomic transaction
diff -r 8b223e308b08 -r 8c3bd7bea667 src/mem/SConscript
--- a/src/mem/SConscript Thu Mar 22 06:34:50 2012 -0400
+++ b/src/mem/SConscript Thu Mar 22 06:36:27 2012 -0400
@@ -40,6 +40,7 @@
Source('mport.cc')
Source('packet.cc')
Source('port.cc')
+Source('packet_queue.cc')
Source('tport.cc')
Source('port_proxy.cc')
Source('fs_translating_port_proxy.cc')
@@ -57,6 +58,7 @@
DebugFlag('LLSC')
DebugFlag('MMU')
DebugFlag('MemoryAccess')
+DebugFlag('PacketQueue')
DebugFlag('ProtocolTrace')
DebugFlag('RubyCache')
diff -r 8b223e308b08 -r 8c3bd7bea667 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc Thu Mar 22 06:34:50 2012 -0400
+++ b/src/mem/cache/base.cc Thu Mar 22 06:36:27 2012 -0400
@@ -54,18 +54,11 @@
using namespace std;
-BaseCache::CacheMasterPort::CacheMasterPort(const std::string &_name,
- BaseCache *_cache,
- const std::string &_label)
- : SimpleTimingPort(_name, _cache, _label)
-{
-}
-
BaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
BaseCache *_cache,
const std::string &_label)
- : SimpleTimingPort(_name, _cache, _label), blocked(false),
- mustSendRetry(false), sendRetryEvent(this)
+ : QueuedPort(_name, _cache, queue), queue(*_cache, *this, _label),
+ blocked(false), mustSendRetry(false), sendRetryEvent(this)
{
}
diff -r 8b223e308b08 -r 8c3bd7bea667 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Thu Mar 22 06:34:50 2012 -0400
+++ b/src/mem/cache/base.hh Thu Mar 22 06:36:27 2012 -0400
@@ -64,8 +64,8 @@
#include "mem/cache/mshr_queue.hh"
#include "mem/mem_object.hh"
#include "mem/packet.hh"
+#include "mem/qport.hh"
#include "mem/request.hh"
-#include "mem/tport.hh"
#include "params/BaseCache.hh"
#include "sim/eventq.hh"
#include "sim/full_system.hh"
@@ -118,7 +118,7 @@
* and the sendDeferredPacket of the timing port is modified to
* consider both the transmit list and the requests from the MSHR.
*/
- class CacheMasterPort : public SimpleTimingPort
+ class CacheMasterPort : public QueuedPort
{
public:
@@ -131,22 +131,31 @@
void requestBus(RequestCause cause, Tick time)
{
DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
- schedSendEvent(time);
+ queue.schedSendEvent(time);
}
+ /**
+ * Schedule the transmissions of a response packet at a given
+ * point in time.
+ *
+ * @param pkt response packet
+ * @param when time to send the response
+ */
void respond(PacketPtr pkt, Tick time) {
- schedSendTiming(pkt, time);
+ queue.schedSendTiming(pkt, time);
}
protected:
CacheMasterPort(const std::string &_name, BaseCache *_cache,
- const std::string &_label);
+ PacketQueue &_queue) :
+ QueuedPort(_name, _cache, _queue)
+ { }
/**
* Memory-side port always snoops.
*
- * return always true
+ * @return always true
*/
virtual bool isSnooping() { return true; }
};
@@ -159,7 +168,7 @@
* incoming requests. If blocked, the port will issue a retry once
* unblocked.
*/
- class CacheSlavePort : public SimpleTimingPort
+ class CacheSlavePort : public QueuedPort
{
public:
@@ -170,8 +179,15 @@
/** Return to normal operation and accept new requests. */
void clearBlocked();
+ /**
+ * Schedule the transmissions of a response packet at a given
+ * point in time.
+ *
+ * @param pkt response packet
+ * @param when time to send the response
+ */
void respond(PacketPtr pkt, Tick time) {
- schedSendTiming(pkt, time);
+ queue.schedSendTiming(pkt, time);
}
protected:
@@ -179,6 +195,9 @@
CacheSlavePort(const std::string &_name, BaseCache *_cache,
const std::string &_label);
+ /** A normal packet queue used to store responses. */
+ PacketQueue queue;
+
bool blocked;
bool mustSendRetry;
diff -r 8b223e308b08 -r 8c3bd7bea667 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Thu Mar 22 06:34:50 2012 -0400
+++ b/src/mem/cache/cache.hh Thu Mar 22 06:36:27 2012 -0400
@@ -109,6 +109,34 @@
};
/**
+ * Override the default behaviour of sendDeferredPacket to enable
+ * the memory-side cache port to also send requests based on the
+ * current MSHR status. This queue has a pointer to our specific
+ * cache implementation and is used by the MemSidePort.
+ */
+ class MemSidePacketQueue : public PacketQueue
+ {
+
+ protected:
+
+ Cache<TagStore> &cache;
+
+ public:
+
+ MemSidePacketQueue(Cache<TagStore> &cache, Port &port,
+ const std::string &label) :
+ PacketQueue(cache, port, label), cache(cache) { }
+
+ /**
+ * Override the normal sendDeferredPacket and do not only
+ * consider the transmit list (used for responses), but also
+ * requests.
+ */
+ virtual void sendDeferredPacket();
+
+ };
+
+ /**
* The memory-side port extends the base cache master port with
* access functions for functional, atomic and timing snoops.
*/
@@ -116,6 +144,9 @@
{
private:
+ /** The cache-specific queue. */
+ MemSidePacketQueue _queue;
+
// a pointer to our specific cache implementation
Cache<TagStore> *cache;
@@ -134,11 +165,6 @@
MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
const std::string &_label);
-
- /**
- * Overload sendDeferredPacket of SimpleTimingPort.
- */
- virtual void sendDeferredPacket();
};
/** Tag and data Storage */
diff -r 8b223e308b08 -r 8c3bd7bea667 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Thu Mar 22 06:34:50 2012 -0400
+++ b/src/mem/cache/cache_impl.hh Thu Mar 22 06:36:27 2012 -0400
@@ -1646,7 +1646,7 @@
template<class TagStore>
void
-Cache<TagStore>::MemSidePort::sendDeferredPacket()
+Cache<TagStore>::MemSidePacketQueue::sendDeferredPacket()
{
// if we have a response packet waiting we have to start with that
if (deferredPacketReady()) {
@@ -1654,7 +1654,7 @@
trySendTiming();
} else {
// check for request packets (requests & writebacks)
- PacketPtr pkt = cache->getTimingPacket();
+ PacketPtr pkt = cache.getTimingPacket();
if (pkt == NULL) {
// can happen if e.g. we attempt a writeback and fail, but
// before the retry, the writeback is eliminated because
@@ -1663,7 +1663,7 @@
} else {
MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState);
- waitingOnRetry = !sendTiming(pkt);
+ waitingOnRetry = !port.sendTiming(pkt);
if (waitingOnRetry) {
DPRINTF(CachePort, "now waiting on a retry\n");
@@ -1679,7 +1679,7 @@
// care about this packet and might override it before
// it gets retried
} else {
- cache->markInService(mshr, pkt);
+ cache.markInService(mshr, pkt);
}
}
}
@@ -1688,7 +1688,7 @@
// next send, not only looking at the response transmit list, but
// also considering when the next MSHR is ready
if (!waitingOnRetry) {
- scheduleSend(cache->nextMSHRReadyTime());
+ scheduleSend(cache.nextMSHRReadyTime());
}
}
@@ -1696,6 +1696,7 @@
Cache<TagStore>::
MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
const std::string &_label)
- : BaseCache::CacheMasterPort(_name, _cache, _label), cache(_cache)
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
