changeset 17f037ad8918 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=17f037ad8918
description:
MEM: Introduce the master/slave port sub-classes in C++
This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.
The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.
The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.
The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.
diffstat:
src/arch/arm/table_walker.cc | 8 +-
src/arch/arm/table_walker.hh | 3 +-
src/arch/arm/tlb.cc | 6 +-
src/arch/arm/tlb.hh | 13 +-
src/arch/x86/interrupts.cc | 17 +-
src/arch/x86/interrupts.hh | 21 +-
src/arch/x86/pagetable_walker.cc | 13 +-
src/arch/x86/pagetable_walker.hh | 9 +-
src/arch/x86/tlb.cc | 6 +-
src/arch/x86/tlb.hh | 12 +-
src/cpu/base.cc | 75 ++---
src/cpu/base.hh | 15 +-
src/cpu/checker/cpu.hh | 6 -
src/cpu/inorder/resources/cache_unit.hh | 2 +-
src/cpu/o3/cpu.hh | 3 +-
src/cpu/o3/lsq_unit.hh | 4 +-
src/cpu/o3/lsq_unit_impl.hh | 2 +-
src/cpu/ozone/OzoneCPU.py | 3 -
src/cpu/ozone/cpu.hh | 2 -
src/cpu/ozone/cpu_impl.hh | 12 -
src/cpu/ozone/front_end.hh | 5 +-
src/cpu/ozone/front_end_impl.hh | 6 -
src/cpu/ozone/lw_lsq.hh | 7 +-
src/cpu/ozone/lw_lsq_impl.hh | 6 -
src/cpu/simple/atomic.cc | 10 +-
src/cpu/simple/atomic.hh | 7 +-
src/cpu/testers/directedtest/RubyDirectedTester.cc | 22 +-
src/cpu/testers/directedtest/RubyDirectedTester.hh | 12 +-
src/cpu/testers/memtest/memtest.cc | 15 +-
src/cpu/testers/memtest/memtest.hh | 9 +-
src/cpu/testers/networktest/networktest.cc | 13 +-
src/cpu/testers/networktest/networktest.hh | 9 +-
src/cpu/testers/rubytest/RubyTester.cc | 21 +-
src/cpu/testers/rubytest/RubyTester.hh | 12 +-
src/dev/copy_engine.cc | 23 +-
src/dev/copy_engine.hh | 5 +-
src/dev/io_device.cc | 19 +-
src/dev/io_device.hh | 16 +-
src/dev/pcidev.hh | 6 +-
src/dev/x86/i82094aa.cc | 4 +-
src/dev/x86/i82094aa.hh | 6 +-
src/dev/x86/intdev.cc | 8 +-
src/dev/x86/intdev.hh | 37 ++-
src/kern/tru64/tru64_events.cc | 4 +-
src/mem/bridge.cc | 45 +-
src/mem/bridge.hh | 21 +-
src/mem/bus.cc | 117 +++++---
src/mem/bus.hh | 103 ++++++-
src/mem/cache/base.cc | 25 +-
src/mem/cache/base.hh | 11 +-
src/mem/cache/builder.cc | 1 -
src/mem/cache/cache.hh | 2 -
src/mem/cache/cache_impl.hh | 15 +-
src/mem/fs_translating_port_proxy.cc | 2 +-
src/mem/fs_translating_port_proxy.hh | 2 +-
src/mem/mem_object.cc | 25 +
src/mem/mem_object.hh | 43 ++-
src/mem/mport.cc | 17 +-
src/mem/mport.hh | 41 ++-
src/mem/physical.cc | 25 +-
src/mem/physical.hh | 4 +-
src/mem/port.cc | 105 +++++++-
src/mem/port.hh | 283 ++++++++++++--------
src/mem/port_proxy.hh | 4 +-
src/mem/qport.hh | 50 +++-
src/mem/ruby/system/RubyPort.cc | 139 ++++++---
src/mem/ruby/system/RubyPort.hh | 25 +-
src/mem/se_translating_port_proxy.cc | 2 +-
src/mem/se_translating_port_proxy.hh | 2 +-
src/mem/tport.cc | 5 +-
src/mem/tport.hh | 2 +-
src/python/swig/pyobject.cc | 37 +-
src/sim/system.cc | 6 +-
src/sim/system.hh | 18 +-
src/sim/tlb.hh | 17 +-
75 files changed, 1043 insertions(+), 665 deletions(-)
diffs (truncated from 3540 to 300 lines):
diff -r e53972f72165 -r 17f037ad8918 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/arm/table_walker.cc Fri Mar 30 09:40:11 2012 -0400
@@ -91,13 +91,13 @@
}
}
-Port*
-TableWalker::getPort(const std::string &if_name, int idx)
+MasterPort&
+TableWalker::getMasterPort(const std::string &if_name, int idx)
{
if (if_name == "port") {
- return &port;
+ return port;
}
- return NULL;
+ return MemObject::getMasterPort(if_name, idx);
}
Fault
diff -r e53972f72165 -r 17f037ad8918 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/arm/table_walker.hh Fri Mar 30 09:40:11 2012 -0400
@@ -358,7 +358,8 @@
virtual unsigned int drain(Event *de);
virtual void resume();
- virtual Port *getPort(const std::string &if_name, int idx = -1);
+ virtual MasterPort& getMasterPort(const std::string &if_name,
+ int idx = -1);
Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
TLB::Translation *_trans, bool timing, bool functional = false);
diff -r e53972f72165 -r 17f037ad8918 src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/arm/tlb.cc Fri Mar 30 09:40:11 2012 -0400
@@ -722,10 +722,10 @@
return fault;
}
-Port*
-TLB::getPort()
+MasterPort*
+TLB::getMasterPort()
{
- return tableWalker->getPort("port");
+ return &tableWalker->getMasterPort("port");
}
diff -r e53972f72165 -r 17f037ad8918 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/arm/tlb.hh Fri Mar 30 09:40:11 2012 -0400
@@ -214,8 +214,17 @@
void regStats();
- // Get the port from the table walker and return it
- virtual Port *getPort();
+ /**
+ * Get the table walker master port. This is used for migrating
+ * port connections during a CPU takeOverFrom() call. For
+ * architectures that do not have a table walker, NULL is
+ * returned, hence the use of a pointer rather than a
+ * reference. For ARM this method will always return a valid port
+ * pointer.
+ *
+ * @return A pointer to the walker master port
+ */
+ virtual MasterPort* getMasterPort();
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.
diff -r e53972f72165 -r 17f037ad8918 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/x86/interrupts.cc Fri Mar 30 09:40:11 2012 -0400
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2008 The Hewlett-Packard Development Company
* All rights reserved.
*
@@ -304,6 +316,9 @@
//
BasicPioDevice::init();
IntDev::init();
+
+ // the slave port has a range so inform the connected master
+ intSlavePort.sendRangeChange();
}
@@ -554,7 +569,7 @@
break;
}
pendingIPIs += apics.size();
- intPort.sendMessage(apics, message, timing);
+ intMasterPort.sendMessage(apics, message, timing);
newVal = regs[APIC_INTERRUPT_COMMAND_LOW];
}
break;
diff -r e53972f72165 -r 17f037ad8918 src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/x86/interrupts.hh Fri Mar 30 09:40:11 2012 -0400
@@ -189,7 +189,7 @@
int initialApicId;
// Port for receiving interrupts
- IntPort intSlavePort;
+ IntSlavePort intSlavePort;
public:
@@ -239,17 +239,20 @@
AddrRangeList getAddrRanges();
AddrRangeList getIntAddrRange();
- Port *getPort(const std::string &if_name, int idx = -1)
+ MasterPort &getMasterPort(const std::string &if_name, int idx = -1)
{
- // a bit of an odd one since there is now two ports in the
- // Python class we also need two ports even if they are
- // identical
if (if_name == "int_master") {
- return &intPort;
- } else if (if_name == "int_slave") {
- return &intSlavePort;
+ return intMasterPort;
}
- return BasicPioDevice::getPort(if_name, idx);
+ return BasicPioDevice::getMasterPort(if_name, idx);
+ }
+
+ SlavePort &getSlavePort(const std::string &if_name, int idx = -1)
+ {
+ if (if_name == "int_slave") {
+ return intSlavePort;
+ }
+ return BasicPioDevice::getSlavePort(if_name, idx);
}
/*
diff -r e53972f72165 -r 17f037ad8918 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/x86/pagetable_walker.cc Fri Mar 30 09:40:11 2012 -0400
@@ -154,11 +154,6 @@
}
void
-Walker::WalkerPort::recvRangeChange()
-{
-}
-
-void
Walker::WalkerPort::recvRetry()
{
walker->recvRetry();
@@ -182,13 +177,13 @@
return port.sendTiming(pkt);
}
-Port *
-Walker::getPort(const std::string &if_name, int idx)
+MasterPort &
+Walker::getMasterPort(const std::string &if_name, int idx)
{
if (if_name == "port")
- return &port;
+ return port;
else
- panic("No page table walker port named %s!\n", if_name);
+ return MemObject::getMasterPort(if_name, idx);
}
void
diff -r e53972f72165 -r 17f037ad8918 src/arch/x86/pagetable_walker.hh
--- a/src/arch/x86/pagetable_walker.hh Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/x86/pagetable_walker.hh Fri Mar 30 09:40:11 2012 -0400
@@ -60,11 +60,11 @@
{
protected:
// Port for accessing memory
- class WalkerPort : public Port
+ class WalkerPort : public MasterPort
{
public:
WalkerPort(const std::string &_name, Walker * _walker) :
- Port(_name, _walker), walker(_walker)
+ MasterPort(_name, _walker), walker(_walker)
{}
protected:
@@ -73,9 +73,8 @@
bool recvTiming(PacketPtr pkt);
Tick recvAtomic(PacketPtr pkt);
void recvFunctional(PacketPtr pkt);
- void recvRangeChange();
void recvRetry();
- bool isSnooping() { return true; }
+ bool isSnooping() const { return true; }
};
friend class WalkerPort;
@@ -166,7 +165,7 @@
RequestPtr req, BaseTLB::Mode mode);
Fault startFunctional(ThreadContext * _tc, Addr &addr,
Addr &pageSize, BaseTLB::Mode mode);
- Port *getPort(const std::string &if_name, int idx = -1);
+ MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
protected:
// The TLB we're supposed to load.
diff -r e53972f72165 -r 17f037ad8918 src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/x86/tlb.cc Fri Mar 30 09:40:11 2012 -0400
@@ -428,10 +428,10 @@
{
}
-Port *
-TLB::getPort()
+MasterPort *
+TLB::getMasterPort()
{
- return walker->getPort("port");
+ return &walker->getMasterPort("port");
}
} // namespace X86ISA
diff -r e53972f72165 -r 17f037ad8918 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh Fri Mar 30 09:38:35 2012 -0400
+++ b/src/arch/x86/tlb.hh Fri Mar 30 09:40:11 2012 -0400
@@ -125,7 +125,17 @@
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
- virtual Port * getPort();
+ /**
+ * Get the table walker master port. This is used for
+ * migrating port connections during a CPU takeOverFrom()
+ * call. For architectures that do not have a table walker,
+ * NULL is returned, hence the use of a pointer rather than a
+ * reference. For X86 this method will always return a valid
+ * port pointer.
+ *
+ * @return A pointer to the walker master port
+ */
+ virtual MasterPort *getMasterPort();
};
}
diff -r e53972f72165 -r 17f037ad8918 src/cpu/base.cc
--- a/src/cpu/base.cc Fri Mar 30 09:38:35 2012 -0400
+++ b/src/cpu/base.cc Fri Mar 30 09:40:11 2012 -0400
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -299,19 +299,19 @@
threadContexts[0]->regStats(name());
}
-Port *
-BaseCPU::getPort(const string &if_name, int idx)
+MasterPort &
+BaseCPU::getMasterPort(const string &if_name, int idx)
{
// Get the right port based on name. This applies to all the
// subclasses of the base CPU and relies on their implementation
// of getDataPort and getInstPort. In all cases there methods
// return a CpuPort pointer.
if (if_name == "dcache_port")
- return &getDataPort();
+ return getDataPort();
else if (if_name == "icache_port")
- return &getInstPort();
+ return getInstPort();
else
- panic("CPU %s has no port named %s\n", name(), if_name);
+ return MemObject::getMasterPort(if_name, idx);
}
Tick
@@ -381,8 +381,6 @@
void
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
