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(Updated April 8, 2012, 9:03 a.m.) Review request for Default. Description ------- MEM: Add the PortId type and a corresponding id field to Port This patch introduces the PortId type, moves the definition of INVALID_PORT_ID to the Port class, and also gives every port an id to reflect the fact that each element in a vector port has an identifier/index. Previously the bus and Ruby testers (and potentially other users of the vector ports) added the id field in their port subclasses, and now this functionality is always present as it is moved to the base class. Diffs (updated) ----- src/cpu/testers/directedtest/RubyDirectedTester.hh a47fd7c2d44e src/cpu/testers/directedtest/RubyDirectedTester.cc a47fd7c2d44e src/cpu/testers/rubytest/RubyTester.hh a47fd7c2d44e src/cpu/testers/rubytest/RubyTester.cc a47fd7c2d44e src/mem/bus.hh a47fd7c2d44e src/mem/bus.cc a47fd7c2d44e src/mem/port.hh a47fd7c2d44e src/mem/port.cc a47fd7c2d44e Diff: http://reviews.gem5.org/r/1138/diff/ Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
