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Review request for Default. Description ------- MEM: Use base class Master/SlavePort pointers in the bus This patch makes some rather trivial simplifications to the bus in that it changes the use of BusMasterPort and BusSlavePort pointers to simply use MasterPort and SlavePort (iterators are also updated accordingly). This change is a step towards a future patch that introduces a separation of the interface and the structural port itself. Diffs ----- src/mem/bus.hh a47fd7c2d44e src/mem/bus.cc a47fd7c2d44e Diff: http://reviews.gem5.org/r/1144/diff/ Testing ------- util/regress all passing (disregarding t1000 and eio) Thanks, Andreas Hansson _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
