Hey Nilay, Hey guys, >> I just updated my repo to the gem5 head, and I'm trying to merge my old >> patches. It looks like the TranslatingPort that used to be the O3CPU >> funcport has changed, and I run into a fatal when trying to run the new >> code. >> >> I'm trying to run simulation with x86 O3CPU, full_system=False (SE mode), >> and using a Ruby cache hierarchy. With the old code, the O3CPU would >> simply use the funcport (before the FS/SE merge) to read from the physmem >> directly (::aside:: this already confuses me, since if the data is >> modified >> in a cache, shouldn't that data be read?). With the updated gem5 code, >> the >> functional access uses the O3CPU's data port, which is connected to a Ruby >> sequencer (more as I would expect), which checks to see if the data is in >> a >> cache before grabbing the data for the read. >> > > I think the first thing that you need look at is as to why the O3 CPU is > trying to make functional accesses. I rolled back the repo to look if there > is any entity by the name funcport, but grep did not provide any results. > Which code are you referring to?
Modifications to the use of the funcPort were made in the following changesets: 8712: http://repo.gem5.org/gem5/rev/7f762428a9f5 8852: http://repo.gem5.org/gem5/rev/c744483edfcf -- Joel Hestness PhD Student, Computer Architecture Dept. of Computer Science, University of Wisconsin - Madison Dept. of Computer Science, University of Texas - Austin http://www.cs.utexas.edu/~hestness _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
