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Review request for Default. Description ------- Changeset 8957:c2d7809a63f0 --------------------------- X86, ISA Parser: runtime read, write conditions for registers This patch does two things. First it allows for operands to make run time decision, whether they should be read/written at all. Secondly, it makes use of this mechanism for x86 isa. The main idea is that each microop, while being used in the microcode, should specify the condition code flags it would read and write. On the basis of this info, at runtime, it would be decided which condition code registers should be read and written. This would help in reducing the extent of RAW dependence while using the o3 cpu with x86. Currently, the flags that would read and written are specified together. Next couple of patches would try to look in to splitting the flags in to read and write sets and split the ccFlagBits register. Diffs ----- src/arch/isa_parser.py 3c7232fec7fd src/arch/x86/insts/microop.hh 3c7232fec7fd src/arch/x86/isa/microops/debug.isa 3c7232fec7fd src/arch/x86/isa/microops/seqop.isa 3c7232fec7fd src/arch/x86/isa/microops/specop.isa 3c7232fec7fd src/arch/x86/isa/operands.isa 3c7232fec7fd Diff: http://reviews.gem5.org/r/1154/diff/ Testing ------- Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
