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Ship it! Ship It! - Ali Saidi On April 11, 2012, 8:25 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1146/ > ----------------------------------------------------------- > > (Updated April 11, 2012, 8:25 a.m.) > > > Review request for Default. > > > Description > ------- > > MEM: Separate requests and responses for timing accesses > > This patch moves send/recvTiming and send/recvTimingSnoop from the > Port base class to the MasterPort and SlavePort, and also splits the > members into separate member functions for requests and responses: > send/recvTimingReq, send/recvTimingResp, and send/recvTimingSnoopReq, > send/recvTimingSnoopResp. A master port sends requests and receives > responses, and also receives snoop requests and sends snoop > responses. A slave port has the reciprocal behaviour as it receives > requests and sends responses, and sends snoop requests and receives > snoop responses. > > For all MemObjects that have only master ports or slave ports (but not > both), e.g. a CPU, or an IO device, this patch merely adds more > clarity to what kind of access is taking place. For example, a CPU > port used to call sendTiming, and will now call > sendTimingReq. Similarly, a response would come back through > recvTiming, which is now recvTimingResp. For the modules that have > both master and slave ports, e.g. the bus, the behaviour was > previously based on branches based on pkt->isRequest(), and this is > now replaced with a direct call to the apprioriate member function > depending on the type of access. Please note that send/recvRetry is > still shared by all the timing accessors and remains in the Port base > class for now (to maintain the current bus functionality and avoid > changing the statistics of all regressions). > > With this patch, the type of packet (request or response) is now well > defined for each type of access, and all asserts on pkt->isRequest() > and pkt->isResponse() are now moved to the appropriate port send > functions. It is also worth noting that sendTimingSnoopReq no longer > returns a boolean, as the semantics do not alow snoop requests to be > rejected or stalled. All these assumptions are now clearly part of the > port interface itself. > > > Diffs > ----- > > src/arch/x86/pagetable_walker.hh 5534a564f6a0 > src/arch/x86/pagetable_walker.cc 5534a564f6a0 > src/cpu/base.hh 5534a564f6a0 > src/cpu/base.cc 5534a564f6a0 > src/cpu/inorder/cpu.hh 5534a564f6a0 > src/cpu/inorder/cpu.cc 5534a564f6a0 > src/cpu/inorder/resources/cache_unit.cc 5534a564f6a0 > src/cpu/o3/cpu.hh 5534a564f6a0 > src/cpu/o3/cpu.cc 5534a564f6a0 > src/cpu/o3/fetch_impl.hh 5534a564f6a0 > src/cpu/o3/lsq.hh 5534a564f6a0 > src/cpu/o3/lsq_impl.hh 5534a564f6a0 > src/cpu/o3/lsq_unit.hh 5534a564f6a0 > src/cpu/o3/lsq_unit_impl.hh 5534a564f6a0 > src/cpu/simple/timing.hh 5534a564f6a0 > src/cpu/simple/timing.cc 5534a564f6a0 > src/cpu/testers/directedtest/InvalidateGenerator.cc 5534a564f6a0 > src/cpu/testers/directedtest/RubyDirectedTester.hh 5534a564f6a0 > src/cpu/testers/directedtest/RubyDirectedTester.cc 5534a564f6a0 > src/cpu/testers/directedtest/SeriesRequestGenerator.cc 5534a564f6a0 > src/cpu/testers/memtest/memtest.hh 5534a564f6a0 > src/cpu/testers/memtest/memtest.cc 5534a564f6a0 > src/cpu/testers/networktest/networktest.hh 5534a564f6a0 > src/cpu/testers/networktest/networktest.cc 5534a564f6a0 > src/cpu/testers/rubytest/Check.cc 5534a564f6a0 > src/cpu/testers/rubytest/RubyTester.hh 5534a564f6a0 > src/cpu/testers/rubytest/RubyTester.cc 5534a564f6a0 > src/dev/io_device.hh 5534a564f6a0 > src/dev/io_device.cc 5534a564f6a0 > src/mem/bridge.hh 5534a564f6a0 > src/mem/bridge.cc 5534a564f6a0 > src/mem/bus.hh 5534a564f6a0 > src/mem/bus.cc 5534a564f6a0 > src/mem/cache/base.hh 5534a564f6a0 > src/mem/cache/cache.hh 5534a564f6a0 > src/mem/cache/cache_impl.hh 5534a564f6a0 > src/mem/mport.hh 5534a564f6a0 > src/mem/packet_queue.hh 5534a564f6a0 > src/mem/packet_queue.cc 5534a564f6a0 > src/mem/port.hh 5534a564f6a0 > src/mem/port.cc 5534a564f6a0 > src/mem/qport.hh 5534a564f6a0 > src/mem/ruby/system/RubyPort.hh 5534a564f6a0 > src/mem/ruby/system/RubyPort.cc 5534a564f6a0 > src/mem/tport.hh 5534a564f6a0 > src/mem/tport.cc 5534a564f6a0 > src/sim/system.hh 5534a564f6a0 > > Diff: http://reviews.gem5.org/r/1146/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
