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Review request for Default. Description ------- Changeset 8973:e70eb4904db5 --------------------------- X86: Split Condition Code register This patch moves the ECF and EZF bits to a separate register. This is just an example patch for discussion. This is how I am proposing we should split the register. If this is acceptable, then ultimately we will have the following registers -- [ZAPS], [OF], [CF], [ECF], [EZF] and [DF]. Diffs ----- src/arch/x86/insts/microregop.hh b9f4e3884951 src/arch/x86/insts/microregop.cc b9f4e3884951 src/arch/x86/isa/microops/debug.isa b9f4e3884951 src/arch/x86/isa/microops/fpop.isa b9f4e3884951 src/arch/x86/isa/microops/regop.isa b9f4e3884951 src/arch/x86/isa/microops/seqop.isa b9f4e3884951 src/arch/x86/isa/microops/specop.isa b9f4e3884951 src/arch/x86/isa/operands.isa b9f4e3884951 src/arch/x86/x86_traits.hh b9f4e3884951 Diff: http://reviews.gem5.org/r/1166/diff/ Testing ------- Boots Linux with atomic cpu. Thanks, Nilay Vaish _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
