I second that. Andreas ________________________________________ From: [email protected] [[email protected]] On Behalf Of Ali Saidi [[email protected]] Sent: Wednesday, May 02, 2012 10:33 PM To: gem5 Developer List Subject: Re: [gem5-dev] changeset in gem5: Regression: Add a test for x86 timing full sy...
This takes 15 minutes to run. I don't think it's quick. Ali On 25.04.2012 23:49, Nilay Vaish wrote: > changeset 6d11b01e2c53 in /z/repo/gem5 > details: http://repo.gem5.org/gem5?cmd=changeset;node=6d11b01e2c53 > description: > Regression: Add a test for x86 timing full system ruby simulation > > diffstat: > > build_opts/X86_MESI_CMP_directory | 3 + > tests/configs/pc-simple-timing-ruby.py | 77 + > tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini | 1383 ++++++++++ > tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats | 708 +++++ > tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simerr | 11 + > tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout | 13 + > tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt | 85 + > tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal | 136 + > util/regress | 2 +- > 9 files changed, 2417 insertions(+), 1 deletions(-) > > diffs (truncated from 2462 to 300 lines): > > diff -r fc2c4db64ded -r 6d11b01e2c53 build_opts/X86_MESI_CMP_directory > --- /dev/null Thu Jan 01 00:00:00 1970 +0000 > +++ b/build_opts/X86_MESI_CMP_directory Wed Apr 25 22:43:36 2012 -0500 > @@ -0,0 +1,3 @@ > +TARGET_ISA = 'x86' > +CPU_MODELS = 'TimingSimpleCPU,O3CPU' > +PROTOCOL = 'MESI_CMP_directory' > diff -r fc2c4db64ded -r 6d11b01e2c53 tests/configs/pc-simple-timing-ruby.py > --- /dev/null Thu Jan 01 00:00:00 1970 +0000 > +++ b/tests/configs/pc-simple-timing-ruby.py Wed Apr 25 22:43:36 2012 -0500 > @@ -0,0 +1,77 @@ > +# Copyright (c) 2012 Mark D. Hill and David A. Wood > +# All rights reserved. > +# > +# Redistribution and use in source and binary forms, with or without > +# modification, are permitted provided that the following conditions are > +# met: redistributions of source code must retain the above copyright > +# notice, this list of conditions and the following disclaimer; > +# redistributions in binary form must reproduce the above copyright > +# notice, this list of conditions and the following disclaimer in the > +# documentation and/or other materials provided with the distribution; > +# neither the name of the copyright holders nor the names of its > +# contributors may be used to endorse or promote products derived from > +# this software without specific prior written permission. > +# > +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS > +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT > +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR > +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT > +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, > +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT > +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, > +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY > +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE > +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > +# > +# Authors: Nilay Vaish > + > +import m5, os, optparse, sys > +from m5.objects import * > +m5.util.addToPath('../configs/common') > +from Benchmarks import SysConfig > +import FSConfig > + > +m5.util.addToPath('../configs/ruby') > +import Ruby > +import Options > + > +# Add the ruby specific and protocol specific options > +parser = optparse.OptionParser() > +Options.addCommonOptions(parser) > +Ruby.define_options(parser) > +(options, args) = parser.parse_args() > + > +# Set the default cache size and associativity to be very small to encourage > +# races between requests and writebacks. > +options.l1d_size="32kB" > +options.l1i_size="32kB" > +options.l2_size="4MB" > +options.l1d_assoc=2 > +options.l1i_assoc=2 > +options.l2_assoc=2 > +options.num_cpus = 2 > + > +#the system > +mdesc = SysConfig(disk = 'linux-x86.img') > +system = FSConfig.makeLinuxX86System('timing', options.num_cpus, > + mdesc=mdesc, Ruby=True) > +system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') > +system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] > +Ruby.create_system(options, system, system.piobus, system._dma_ports) > + > +for (i, cpu) in enumerate(system.cpu): > + # create the interrupt controller > + cpu.createInterruptController() > + # Tie the cpu ports to the correct ruby system ports > + cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave > + cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave > + cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave > + cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave > + cpu.interrupts.pio = system.piobus.master > + cpu.interrupts.int_master = system.piobus.slave > + cpu.interrupts.int_slave = system.piobus.master > + cpu.clock = '2GHz' > + > +root = Root(full_system = True, system = system) > +m5.ticks.setGlobalFrequency('1THz') > diff -r fc2c4db64ded -r 6d11b01e2c53 tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini > --- /dev/null Thu Jan 01 00:00:00 1970 +0000 > +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini Wed Apr 25 22:43:36 2012 -0500 > @@ -0,0 +1,1383 @@ > +[root] > +type=Root > +children=system > +full_system=true > +time_sync_enable=false > +time_sync_period=100000000000 > +time_sync_spin_threshold=100000000 > + > +[system] > +type=LinuxX86System > +children=acpi_description_table_pointer cpu0 cpu1 dir_cntrl0 dma_cntrl0 e820_table intel_mp_pointer intel_mp_table intrctrl l1_cntrl0 l1_cntrl1 l2_cntrl0 pc physmem piobus ruby smbios_table sys_port_proxy > +acpi_description_table_pointer=system.acpi_description_table_pointer > +boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1 > +e820_table=system.e820_table > +init_param=0 > +intel_mp_pointer=system.intel_mp_pointer > +intel_mp_table=system.intel_mp_table > +kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp > +load_addr_mask=18446744073709551615 > +mem_mode=timing > +memories=system.physmem > +num_work_ids=16 > +readfile=tests/halt.sh > +smbios_table=system.smbios_table > +symbolfile= > +work_begin_ckpt_count=0 > +work_begin_cpu_id_exit=-1 > +work_begin_exit_count=0 > +work_cpus_ckpt_count=0 > +work_end_ckpt_count=0 > +work_end_exit_count=0 > +work_item_id=-1 > +system_port=system.sys_port_proxy.slave[0] > + > +[system.acpi_description_table_pointer] > +type=X86ACPIRSDP > +children=xsdt > +oem_id= > +revision=2 > +rsdt=Null > +xsdt=system.acpi_description_table_pointer.xsdt > + > +[system.acpi_description_table_pointer.xsdt] > +type=X86ACPIXSDT > +creator_id= > +creator_revision=0 > +entries= > +oem_id= > +oem_revision=0 > +oem_table_id= > + > +[system.cpu0] > +type=TimingSimpleCPU > +children=dtb interrupts itb tracer > +checker=Null > +clock=500 > +cpu_id=0 > +defer_registration=false > +do_checkpoint_insts=true > +do_quiesce=true > +do_statistics_insts=true > +dtb=system.cpu0.dtb > +function_trace=false > +function_trace_start=0 > +interrupts=system.cpu0.interrupts > +itb=system.cpu0.itb > +max_insts_all_threads=0 > +max_insts_any_thread=0 > +max_loads_all_threads=0 > +max_loads_any_thread=0 > +numThreads=1 > +phase=0 > +profile=0 > +progress_interval=0 > +system=system > +tracer=system.cpu0.tracer > +workload= > +dcache_port=system.l1_cntrl0.sequencer.slave[1] > +icache_port=system.l1_cntrl0.sequencer.slave[0] > + > +[system.cpu0.dtb] > +type=X86TLB > +children=walker > +size=64 > +walker=system.cpu0.dtb.walker > + > +[system.cpu0.dtb.walker] > +type=X86PagetableWalker > +system=system > +port=system.l1_cntrl0.sequencer.slave[3] > + > +[system.cpu0.interrupts] > +type=X86LocalApic > +int_latency=1000 > +pio_addr=2305843009213693952 > +pio_latency=1000 > +system=system > +int_master=system.piobus.slave[4] > +int_slave=system.piobus.master[19] > +pio=system.piobus.master[18] > + > +[system.cpu0.itb] > +type=X86TLB > +children=walker > +size=64 > +walker=system.cpu0.itb.walker > + > +[system.cpu0.itb.walker] > +type=X86PagetableWalker > +system=system > +port=system.l1_cntrl0.sequencer.slave[2] > + > +[system.cpu0.tracer] > +type=ExeTracer > + > +[system.cpu1] > +type=TimingSimpleCPU > +children=dtb interrupts itb tracer > +checker=Null > +clock=500 > +cpu_id=1 > +defer_registration=false > +do_checkpoint_insts=true > +do_quiesce=true > +do_statistics_insts=true > +dtb=system.cpu1.dtb > +function_trace=false > +function_trace_start=0 > +interrupts=system.cpu1.interrupts > +itb=system.cpu1.itb > +max_insts_all_threads=0 > +max_insts_any_thread=0 > +max_loads_all_threads=0 > +max_loads_any_thread=0 > +numThreads=1 > +phase=0 > +profile=0 > +progress_interval=0 > +system=system > +tracer=system.cpu1.tracer > +workload= > +dcache_port=system.l1_cntrl1.sequencer.slave[1] > +icache_port=system.l1_cntrl1.sequencer.slave[0] > + > +[system.cpu1.dtb] > +type=X86TLB > +children=walker > +size=64 > +walker=system.cpu1.dtb.walker > + > +[system.cpu1.dtb.walker] > +type=X86PagetableWalker > +system=system > +port=system.l1_cntrl1.sequencer.slave[3] > + > +[system.cpu1.interrupts] > +type=X86LocalApic > +int_latency=1000 > +pio_addr=2305843009213693952 > +pio_latency=1000 > +system=system > +int_master=system.piobus.slave[5] > +int_slave=system.piobus.master[21] > +pio=system.piobus.master[20] > + > +[system.cpu1.itb] > +type=X86TLB > +children=walker > +size=64 > +walker=system.cpu1.itb.walker > + > +[system.cpu1.itb.walker] > +type=X86PagetableWalker > +system=system > +port=system.l1_cntrl1.sequencer.slave[2] > + > +[system.cpu1.tracer] > +type=ExeTracer > + > +[system.dir_cntrl0] > +type=Directory_Controller > +children=directory memBuffer > +buffer_size=0 > +cntrl_id=3 > +directory=system.dir_cntrl0.directory > +directory_latency=6 > +memBuffer=system.dir_cntrl0.memBuffer > +number_of_TBEs=256 > +recycle_latency=10 > +ruby_system=system.ruby > +to_mem_ctrl_latency=1 > +transitions_per_cycle=32 > +version=0 > + > +[system.dir_cntrl0.directory] > +type=RubyDirectoryMemory > +map_levels=4 > +numa_high_bit=6 > +size=134217728 > +use_map=false > +version=0 > + > +[system.dir_cntrl0.memBuffer] > +type=RubyMemoryControl > +bank_bit_0=8 > +bank_busy_time=11 > +bank_queue_size=12 > +banks_per_rank=8 > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
