changeset 528f0fa80f76 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=528f0fa80f76
description:
gem5: Fix a number of incorrect case statements
diffstat:
src/arch/arm/miscregs.cc | 4 ++++
src/dev/arm/rv_ctrl.cc | 1 +
src/mem/cache/mshr.cc | 16 ++++++++++++----
3 files changed, 17 insertions(+), 4 deletions(-)
diffs (72 lines):
diff -r a5add07e066c -r 528f0fa80f76 src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc Thu May 10 18:04:26 2012 -0500
+++ b/src/arch/arm/miscregs.cc Thu May 10 18:04:26 2012 -0500
@@ -392,6 +392,7 @@
case 7:
return MISCREG_PMCEID1;
}
+ break;
case 13:
switch (opc2) {
case 0:
@@ -401,6 +402,7 @@
case 2:
return MISCREG_PMXEVCNTR;
}
+ break;
case 14:
switch (opc2) {
case 0:
@@ -410,6 +412,7 @@
case 2:
return MISCREG_PMINTENCLR;
}
+ break;
}
} else if (opc1 == 1) {
switch (crm) {
@@ -422,6 +425,7 @@
crn,crm, opc1,opc2);
break;
}
+ break;
default:
return MISCREG_L2LATENCY;
}
diff -r a5add07e066c -r 528f0fa80f76 src/dev/arm/rv_ctrl.cc
--- a/src/dev/arm/rv_ctrl.cc Thu May 10 18:04:26 2012 -0500
+++ b/src/dev/arm/rv_ctrl.cc Thu May 10 18:04:26 2012 -0500
@@ -105,6 +105,7 @@
break;
case CfgStat:
pkt->set<uint32_t>(1);
+ break;
default:
warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
daddr);
diff -r a5add07e066c -r 528f0fa80f76 src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc Thu May 10 18:04:26 2012 -0500
+++ b/src/mem/cache/mshr.cc Thu May 10 18:04:26 2012 -0500
@@ -161,10 +161,18 @@
for (ConstIterator i = begin(); i != end_i; ++i) {
const char *s;
switch (i->source) {
- case Target::FromCPU: s = "FromCPU";
- case Target::FromSnoop: s = "FromSnoop";
- case Target::FromPrefetcher: s = "FromPrefetcher";
- default: s = "";
+ case Target::FromCPU:
+ s = "FromCPU";
+ break;
+ case Target::FromSnoop:
+ s = "FromSnoop";
+ break;
+ case Target::FromPrefetcher:
+ s = "FromPrefetcher";
+ break;
+ default:
+ s = "";
+ break;
}
ccprintf(os, "%s%s: ", prefix, s);
i->pkt->print(os, verbosity, "");
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