changeset c264de5ccb61 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=c264de5ccb61
description:
ARM: pl011 raw interrupt fix
Raw interrupt was not being set when interrupt was disabled.
This patch sets the raw interrupt regardless of the mask.
diffstat:
src/dev/arm/pl011.cc | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diffs (15 lines):
diff -r 6c2381ecdfbc -r c264de5ccb61 src/dev/arm/pl011.cc
--- a/src/dev/arm/pl011.cc Thu May 10 18:04:28 2012 -0500
+++ b/src/dev/arm/pl011.cc Thu May 10 18:04:28 2012 -0500
@@ -185,9 +185,10 @@
term->out(data & 0xFF);
+ //raw interrupt is set regardless of imsc.txim
+ rawInt.txim = 1;
if (imsc.txim) {
DPRINTF(Uart, "TX int enabled, scheduling interruptt\n");
- rawInt.txim = 1;
if (!intEvent.scheduled())
schedule(intEvent, curTick() + intDelay);
}
_______________________________________________
gem5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/gem5-dev
