changeset f681719e2e99 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=f681719e2e99
description:
ARM: update stats for clock frequency fix.
diffstat:
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
| 6 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
| 10 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
| 1433 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
| 1 -
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
| 10 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
| 2554 +++++-----
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
| 0
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
| 1 -
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
| 10 +-
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
| 1411 ++--
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
| 878 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
| 428 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
| 1638 +++---
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
| 0
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
| 788 +-
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
| 0
23 files changed, 4604 insertions(+), 4604 deletions(-)
diffs (truncated from 10257 to 300 lines):
diff -r e2364b281ee3 -r f681719e2e99
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
Thu May 10 18:04:28 2012 -0500
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
Thu May 10 18:04:29 2012 -0500
@@ -14,9 +14,11 @@
warn: 5664849500: Instruction results do not match! (Values may not actually
be integers) Inst: 0x36c4, checker: 0x36c8
warn: 5704830500: Instruction results do not match! (Values may not actually
be integers) Inst: 0x3604, checker: 0x3608
warn: 5721485500: Instruction results do not match! (Values may not actually
be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6170779000: Instruction results do not match! (Values may not actually
be integers) Inst: 0x34f0, checker: 0x34f8
warn: LCD dual screen mode not supported
-warn: 53386624000: Instruction results do not match! (Values may not actually
be integers) Inst: 0x19dc, checker: 0x1a04
-warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
+warn: 53396857000: Instruction results do not match! (Values may not actually
be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 55147144000: Instruction results do not match! (Values may not actually
be integers) Inst: 0x80d0, checker: 0xc71f6fc8
+warn: 55147144000: Instruction results do not match! (Values may not actually
be integers) Inst: 0x71ef0, checker: 0x60000013
warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
warn: Returning thumbEE disabled for now since we don't support CP14config
registers and jumping to ThumbEE vectors
warn: instruction 'mcr icialluis' unimplemented
diff -r e2364b281ee3 -r f681719e2e99
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
Thu May 10 18:04:28 2012 -0500
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
Thu May 10 18:04:29 2012 -0500
@@ -1,12 +1,12 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:17:37
-gem5 started May 8 2012 17:08:48
-gem5 executing on piton
+gem5 compiled May 10 2012 12:36:36
+gem5 started May 10 2012 12:41:59
+gem5 executing on u200540-lin
command line: build/ARM/gem5.opt -d
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re
tests/run.py
build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at:
/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2501676293500 because m5_exit instruction encountered
+Exiting @ tick 2501685689500 because m5_exit instruction encountered
diff -r e2364b281ee3 -r f681719e2e99
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Thu May 10 18:04:28 2012 -0500
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
Thu May 10 18:04:29 2012 -0500
@@ -1,26 +1,26 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.501676 #
Number of seconds simulated
-sim_ticks 2501676293500 #
Number of ticks simulated
-final_tick 2501676293500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 2.501686 #
Number of seconds simulated
+sim_ticks 2501685689500 #
Number of ticks simulated
+final_tick 2501685689500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 32851 #
Simulator instruction rate (inst/s)
-host_op_rate 42433 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1382341341 #
Simulator tick rate (ticks/s)
-host_mem_usage 388632 #
Number of bytes of host memory used
-host_seconds 1809.74 #
Real time elapsed on the host
-sim_insts 59451291 #
Number of instructions simulated
-sim_ops 76792341 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read 129652968 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read 1121024 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written 9585096 #
Number of bytes written to this memory
-system.physmem.num_reads 14979455 #
Number of read requests responded to by this memory
-system.physmem.num_writes 856659 #
Number of write requests responded to by this memory
+host_inst_rate 54158 #
Simulator instruction rate (inst/s)
+host_op_rate 69928 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2274069684 #
Simulator tick rate (ticks/s)
+host_mem_usage 384504 #
Number of bytes of host memory used
+host_seconds 1100.09 #
Real time elapsed on the host
+sim_insts 59579009 #
Number of instructions simulated
+sim_ops 76926775 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read 129658608 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read 1119872 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written 9585736 #
Number of bytes written to this memory
+system.physmem.num_reads 14980335 #
Number of read requests responded to by this memory
+system.physmem.num_writes 856669 #
Number of write requests responded to by this memory
system.physmem.num_other 0 #
Number of other requests responded to by this memory
-system.physmem.bw_read 51826437 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 448109 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 3831469 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55657906 #
Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read 51828496 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 447647 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 3831711 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 55660207 #
Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read 64 #
Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read 64 #
Number of instructions bytes read from this memory
system.realview.nvmem.bytes_written 0 #
Number of bytes written to this memory
@@ -30,141 +30,141 @@
system.realview.nvmem.bw_read 26 #
Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read 26 #
Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total 26 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 119784 #
number of replacements
-system.l2c.tagsinuse 25999.615357 #
Cycle average of tags in use
-system.l2c.total_refs 1826145 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 150763 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 12.112687 #
Average number of references to valid blocks.
+system.l2c.replacements 119797 #
number of replacements
+system.l2c.tagsinuse 26022.811009 #
Cycle average of tags in use
+system.l2c.total_refs 1834134 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 150735 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 12.167937 #
Average number of references to valid blocks.
system.l2c.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 14272.421964 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker 65.344146 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 0.932012 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 6169.201034 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 5491.716201 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.217780 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker 0.000997 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.itb.walker 0.000014 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.094135 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.083797 #
Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.396723 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker 141919 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker 12116 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst 995766 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 377927 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 1527728 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 634955 #
number of Writeback hits
-system.l2c.Writeback_hits::total 634955 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 46 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 46 #
number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu.data 7 #
number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 7 #
number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 105770 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 105770 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker 141919 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker 12116 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst 995766 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 483697 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 1633498 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker 141919 #
number of overall hits
-system.l2c.overall_hits::cpu.itb.walker 12116 #
number of overall hits
-system.l2c.overall_hits::cpu.inst 995766 #
number of overall hits
-system.l2c.overall_hits::cpu.data 483697 #
number of overall hits
-system.l2c.overall_hits::total 1633498 #
number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker 157 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker 13 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst 17392 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 19166 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 36728 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 3302 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 3302 #
number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu.data 3 #
number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 3 #
number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 140335 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 140335 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker 157 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker 13 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst 17392 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 159501 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 177063 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker 157 #
number of overall misses
-system.l2c.overall_misses::cpu.itb.walker 13 #
number of overall misses
-system.l2c.overall_misses::cpu.inst 17392 #
number of overall misses
-system.l2c.overall_misses::cpu.data 159501 #
number of overall misses
-system.l2c.overall_misses::total 177063 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker 8196500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker 677000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst 910933000 #
number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data 1001503500 #
number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 1921310000 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data 1203000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 1203000 #
number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu.data 52000
# number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 52000
# number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data 7367598500
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7367598500 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker 8196500
# number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker 677000
# number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst 910933000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data 8369102000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 9288908500 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker 8196500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker 677000
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst 910933000 #
number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data 8369102000 #
number of overall miss cycles
-system.l2c.overall_miss_latency::total 9288908500 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker 142076
# number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker 12129
# number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst 1013158 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 397093 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1564456 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 634955 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 634955 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 3348 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 3348 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu.data 10
# number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 10 #
number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 246105 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 246105 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker 142076
# number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker 12129
# number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst 1013158 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 643198 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1810561 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker 142076
# number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker 12129
# number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 1013158 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 643198 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1810561 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.001105
# miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001072
# miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.017166 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data 0.048266 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.986260 #
miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.300000
# miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.570224 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker 0.001105
# miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker 0.001072
# miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst 0.017166 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.247981 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker 0.001105
# miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker 0.001072
# miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst 0.017166 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data 0.247981 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52207.006369
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52076.923077
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52376.552438
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52254.174058
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 364.324652
# average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu.data 17333.333333
# average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52500.078384
# average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52207.006369
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker 52076.923077
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52376.552438
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52470.529965
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52207.006369
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker 52076.923077
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52376.552438
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52470.529965
# average overall miss latency
+system.l2c.occ_blocks::writebacks 14260.921168 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 79.122472 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 1.014068 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 6176.146101 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5505.607200 #
Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.217604 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker 0.001207 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker 0.000015 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.094241 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.084009 #
Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.397077 #
Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 144170 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 12492 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 1001175 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 378296 #
number of ReadReq hits
+system.l2c.ReadReq_hits::total 1536133 #
number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 635023 #
number of Writeback hits
+system.l2c.Writeback_hits::total 635023 #
number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data 45 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 45 #
number of UpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data 8 #
number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::total 8 #
number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data 105875 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 105875 #
number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker 144170 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker 12492 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst 1001175 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 484171 #
number of demand (read+write) hits
+system.l2c.demand_hits::total 1642008 #
number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker 144170 #
number of overall hits
+system.l2c.overall_hits::cpu.itb.walker 12492 #
number of overall hits
+system.l2c.overall_hits::cpu.inst 1001175 #
number of overall hits
+system.l2c.overall_hits::cpu.data 484171 #
number of overall hits
+system.l2c.overall_hits::total 1642008 #
number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker 189 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker 14 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 17378 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 19180 #
number of ReadReq misses
+system.l2c.ReadReq_misses::total 36761 #
number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data 3300 #
number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 3300 #
number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data 5 #
number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 5 #
number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data 140292 #
number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 140292 #
number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker 189 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker 14 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst 17378 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data 159472 #
number of demand (read+write) misses
+system.l2c.demand_misses::total 177053 #
number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker 189 #
number of overall misses
+system.l2c.overall_misses::cpu.itb.walker 14 #
number of overall misses
+system.l2c.overall_misses::cpu.inst 17378 #
number of overall misses
+system.l2c.overall_misses::cpu.data 159472 #
number of overall misses
+system.l2c.overall_misses::total 177053 #
number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker 9850500
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker 752000
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst 910079500 #
number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data 1002096000 #
number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 1922778000 #
number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data 996000
# number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 996000 #
number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu.data 104000
# number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 104000
# number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data 7365557000
# number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7365557000 #
number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker 9850500
# number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker 752000
# number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst 910079500 #
number of demand (read+write) miss cycles
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