Hi, The MIPS code should work fine on InOrder. Are you sure it's the cross compiler or is there something going on with the model? If it's the compiler you can try rolling back to previous known working versions of the MIPS cross compiler (check to see what people on the mailing list have used...Deyuan Guo?).
I'd first see if the model is breaking somehow. Run the same binary on the SimpleCPU. If it works, then likely there is something happening with the syscall arguments that is causing that bad allocation error you were getting. That can be fixed within the model if that's the problem. As for ARM, there have been strides to getting it to work. Erik Tomusk did a good job getting the 1st issue resolved which was timing TLB translation in InOrder. This enables the ARM model to use the HW page table walker. The second issue is that the InOrder model is not currently supporting microcoded ISAs. I hope to make an initial effort/patch toward this next week as interest in this ramping up from various developers. Hopefully, then if someone wants to take this task on then I can at the very least be in a advisory rule to help work out the kinks. I'd think that's going to be a 2-4 week effort though when you include debugging time. On Wed, May 16, 2012 at 4:50 PM, Tarun Pondicherry <[email protected]>wrote: > Hi, > > I'm interested in using an in order ARM model. Based on the documentation > I've found and my search through the lists and Mercurial, it seems that > this is not supported. I've seen some traffic on this topic in the past > couple months, and was wondering if anyone had (even a half working) patch > for this to get started with or could point me to a good place to start. > > Our higher level goal is to explore some cache optimizations on in order > cores. Our code is generated using LLVM and cross compiled to a gem5 > target. Since, LLVM does not support Alpha well, we would like to use ARM > (preferred) or MIPS. We did try using MIPS as well, but the code generated > by the cs cross compiler fails with std::bad_alloc during a call to writev > in system_emul.hh because it tries to allocate an array of length 0. The > sample binary does run to completion. > > I would appreciate help in moving us forward with either patching an in > order model for ARM or getting MIPS to run binaries generated by cs cross > compiler. > > Thanks, > Tarun > _______________________________________________ > gem5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/gem5-dev > -- - Korey _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
