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src/mem/cache/cache_impl.hh <http://reviews.gem5.org/r/1207/#comment3089> Seems fine for the normal case, but if you hookde two caches up directly, would this break? - Ali Saidi On May 18, 2012, 9:12 a.m., Andreas Hansson wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1207/ > ----------------------------------------------------------- > > (Updated May 18, 2012, 9:12 a.m.) > > > Review request for Default. > > > Description > ------- > > Cache: Remove redundant check for uncacheable snoops > > This patch removes the check for uncacheable requests in the cache > snoop timing/atomic access methods. This check is now taken care of by > the bus, and there is no need to perform it also in the caches. > > > Diffs > ----- > > src/mem/cache/cache_impl.hh 7100059f7bfd > > Diff: http://reviews.gem5.org/r/1207/diff/ > > > Testing > ------- > > util/regress all passing (disregarding t1000 and eio) > > > Thanks, > > Andreas Hansson > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
