changeset 7891b96e1526 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=7891b96e1526
description:
X86: Split Condition Code register
This patch moves the ECF and EZF bits to individual registers (ecfBit
and
ezfBit) and the CF and OF bits to cfofFlag registers. This is being done
so as to lower the read after write dependencies on the the condition
code
register. Ultimately we will have the following registers [ZAPS], [OF],
[CF], [ECF], [EZF] and [DF]. Note that this is only one part of the
solution for lowering the dependencies. The other part will check
whether
or not the condition code register needs to be actually read. This would
be done through a separate patch.
diffstat:
src/arch/x86/isa/microops/debug.isa | 3 +-
src/arch/x86/isa/microops/fpop.isa | 16 +-
src/arch/x86/isa/microops/mediaop.isa | 13 +-
src/arch/x86/isa/microops/regop.isa | 314 +++++++++++++++++++++++----------
src/arch/x86/isa/microops/seqop.isa | 6 +-
src/arch/x86/isa/microops/specop.isa | 3 +-
src/arch/x86/isa/operands.isa | 7 +-
src/arch/x86/regs/misc.hh | 3 +
src/arch/x86/x86_traits.hh | 2 +-
9 files changed, 251 insertions(+), 116 deletions(-)
diffs (truncated from 758 to 300 lines):
diff -r d45a02bd5391 -r 7891b96e1526 src/arch/x86/isa/microops/debug.isa
--- a/src/arch/x86/isa/microops/debug.isa Sat May 19 04:32:25 2012 -0700
+++ b/src/arch/x86/isa/microops/debug.isa Tue May 22 11:29:53 2012 -0500
@@ -141,7 +141,8 @@
{"code": "",
"func": func,
"func_num": "GenericISA::M5DebugFault::%s" % func_num,
- "cond_test": "checkCondition(ccFlagBits, cc)"})
+ "cond_test": "checkCondition(ccFlagBits | cfofBits | \
+ ecfBit | ezfBit, cc)"})
exec_output += MicroDebugExecute.subst(iop)
header_output += MicroDebugDeclare.subst(iop)
decoder_output += MicroDebugConstructor.subst(iop)
diff -r d45a02bd5391 -r 7891b96e1526 src/arch/x86/isa/microops/fpop.isa
--- a/src/arch/x86/isa/microops/fpop.isa Sat May 19 04:32:25 2012 -0700
+++ b/src/arch/x86/isa/microops/fpop.isa Tue May 22 11:29:53 2012 -0500
@@ -215,7 +215,8 @@
spm, SetStatus, dataSize)
code = 'FpDestReg_uqw = FpSrcReg1_uqw;'
else_code = 'FpDestReg_uqw = FpDestReg_uqw;'
- cond_check = "checkCondition(ccFlagBits, src2)"
+ cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
+ src2)"
class Xorfp(FpOp):
code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;'
@@ -283,12 +284,15 @@
// Less than 0 0 1
// Equal 1 0 0
// OF = SF = AF = 0
- ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit |
- ZFBit | PFBit | CFBit);
- if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2))
- ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit);
+ ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
+ cfofBits = cfofBits & ~(OFBit | CFBit);
+
+ if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2)) {
+ ccFlagBits = ccFlagBits | (ZFBit | PFBit);
+ cfofBits = cfofBits | CFBit;
+ }
else if(FpSrcReg1 < FpSrcReg2)
- ccFlagBits = ccFlagBits | CFBit;
+ cfofBits = cfofBits | CFBit;
else if(FpSrcReg1 == FpSrcReg2)
ccFlagBits = ccFlagBits | ZFBit;
'''
diff -r d45a02bd5391 -r 7891b96e1526 src/arch/x86/isa/microops/mediaop.isa
--- a/src/arch/x86/isa/microops/mediaop.isa Sat May 19 04:32:25 2012 -0700
+++ b/src/arch/x86/isa/microops/mediaop.isa Tue May 22 11:29:53 2012 -0500
@@ -1490,12 +1490,15 @@
// Less than 0 0 1
// Equal 1 0 0
// OF = SF = AF = 0
- ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit |
- ZFBit | PFBit | CFBit);
- if (std::isnan(arg1) || std::isnan(arg2))
- ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit);
+ ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit);
+ cfofBits = cfofBits & ~(OFBit | CFBit);
+
+ if (std::isnan(arg1) || std::isnan(arg2)) {
+ ccFlagBits = ccFlagBits | (ZFBit | PFBit);
+ cfofBits = cfofBits | CFBit;
+ }
else if(arg1 < arg2)
- ccFlagBits = ccFlagBits | CFBit;
+ cfofBits = cfofBits | CFBit;
else if(arg1 == arg2)
ccFlagBits = ccFlagBits | ZFBit;
'''
diff -r d45a02bd5391 -r 7891b96e1526 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa Sat May 19 04:32:25 2012 -0700
+++ b/src/arch/x86/isa/microops/regop.isa Tue May 22 11:29:53 2012 -0500
@@ -438,26 +438,42 @@
flag_code = '''
//Don't have genFlags handle the OF or CF bits
uint64_t mask = CFBit | ECFBit | OFBit;
- ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | ezfBit, ext & ~mask,
+ result, psrc1, op2);
+ ezfBit = newFlags & EZFBit;
+ ccFlagBits = newFlags & ccFlagMask;
+
//If a logic microop wants to set these, it wants to set them to 0.
- ccFlagBits &= ~(CFBit & ext);
- ccFlagBits &= ~(ECFBit & ext);
- ccFlagBits &= ~(OFBit & ext);
+ cfofBits = cfofBits & ~((CFBit | OFBit) & ext);
+ ecfBit = ecfBit & ~(ECFBit & ext);
'''
class FlagRegOp(RegOp):
abstract = True
- flag_code = \
- "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
+ flag_code = '''
+ uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
+ ezfBit, ext, result, psrc1, op2);
+ cfofBits = newFlags & cfofMask;
+ ecfBit = newFlags & ECFBit;
+ ezfBit = newFlags & EZFBit;
+ ccFlagBits = newFlags & ccFlagMask;
+ '''
class SubRegOp(RegOp):
abstract = True
- flag_code = \
- "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2,
true);"
+ flag_code = '''
+ uint64_t newFlags = genFlags(ccFlagBits | cfofBits | ecfBit |
+ ezfBit, ext, result, psrc1, ~op2, true);
+ cfofBits = newFlags & cfofMask;
+ ecfBit = newFlags & ECFBit;
+ ezfBit = newFlags & EZFBit;
+ ccFlagBits = newFlags & ccFlagMask;
+ '''
class CondRegOp(RegOp):
abstract = True
- cond_check = "checkCondition(ccFlagBits, ext)"
+ cond_check = "checkCondition(ccFlagBits | cfofBits | ecfBit | ezfBit, \
+ ext)"
cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];"
class RdRegOp(RegOp):
@@ -484,21 +500,21 @@
class Adc(FlagRegOp):
code = '''
- CCFlagBits flags = ccFlagBits;
+ CCFlagBits flags = cfofBits;
DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf),
dataSize);
'''
big_code = '''
- CCFlagBits flags = ccFlagBits;
+ CCFlagBits flags = cfofBits;
DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
'''
class Sbb(SubRegOp):
code = '''
- CCFlagBits flags = ccFlagBits;
+ CCFlagBits flags = cfofBits;
DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf),
dataSize);
'''
big_code = '''
- CCFlagBits flags = ccFlagBits;
+ CCFlagBits flags = cfofBits;
DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
'''
@@ -536,9 +552,11 @@
flag_code = '''
if ((-ProdHi & mask(dataSize * 8)) !=
bits(ProdLow, dataSize * 8 - 1)) {
- ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
+ cfofBits = cfofBits | (ext & (CFBit | OFBit));
+ ecfBit = ecfBit | (ext & ECFBit);
} else {
- ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
+ cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
+ ecfBit = ecfBit & ~(ext & ECFBit);
}
'''
@@ -557,9 +575,11 @@
'''
flag_code = '''
if (ProdHi) {
- ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit));
+ cfofBits = cfofBits | (ext & (CFBit | OFBit));
+ ecfBit = ecfBit | (ext & ECFBit);
} else {
- ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit));
+ cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
+ ecfBit = ecfBit & ~(ext & ECFBit);
}
'''
@@ -658,9 +678,9 @@
big_code = divCode % "DestReg = remaining & mask(dataSize * 8);"
flag_code = '''
if (remaining == 0)
- ccFlagBits = ccFlagBits | (ext & EZFBit);
+ ezfBit = ezfBit | (ext & EZFBit);
else
- ccFlagBits = ccFlagBits & ~(ext & EZFBit);
+ ezfBit = ezfBit & ~(ext & EZFBit);
'''
class Divq(RdRegOp):
@@ -691,22 +711,31 @@
if (shiftAmt) {
//Zero out any flags we might modify. This way we only have to
//worry about setting them.
- ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
+ cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
+ ecfBit = ecfBit & ~(ext & ECFBit);
+
int CFBits = 0;
//Figure out if we -would- set the CF bits if requested.
if (shiftAmt <= dataSize * 8 &&
bits(SrcReg1, dataSize * 8 - shiftAmt)) {
CFBits = 1;
}
+
//If some combination of the CF bits need to be set, set them.
- if ((ext & (CFBit | ECFBit)) && CFBits)
- ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
+ if ((ext & (CFBit | ECFBit)) && CFBits) {
+ cfofBits = cfofBits | (ext & CFBit);
+ ecfBit = ecfBit | (ext & ECFBit);
+ }
+
//Figure out what the OF bit should be.
if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 -
1)))
- ccFlagBits = ccFlagBits | OFBit;
+ cfofBits = cfofBits | OFBit;
+
//Use the regular mechanisms to calculate the other flags.
- ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit |
OFBit),
- DestReg, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
+ ezfBit = newFlags & EZFBit;
+ ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -729,19 +758,26 @@
if (shiftAmt) {
//Zero out any flags we might modify. This way we only have to
//worry about setting them.
- ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
+ cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
+ ecfBit = ecfBit & ~(ext & ECFBit);
+
//If some combination of the CF bits need to be set, set them.
if ((ext & (CFBit | ECFBit)) &&
shiftAmt <= dataSize * 8 &&
bits(SrcReg1, shiftAmt - 1)) {
- ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
+ cfofBits = cfofBits | (ext & CFBit);
+ ecfBit = ecfBit | (ext & ECFBit);
}
+
//Figure out what the OF bit should be.
if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1))
- ccFlagBits = ccFlagBits | OFBit;
+ cfofBits = cfofBits | OFBit;
+
//Use the regular mechanisms to calculate the other flags.
- ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit |
OFBit),
- DestReg, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
+ ezfBit = newFlags & EZFBit;
+ ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -766,17 +802,23 @@
if (shiftAmt) {
//Zero out any flags we might modify. This way we only have to
//worry about setting them.
- ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
+ cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
+ ecfBit = ecfBit & ~(ext & ECFBit);
+
//If some combination of the CF bits need to be set, set them.
uint8_t effectiveShift =
(shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8);
if ((ext & (CFBit | ECFBit)) &&
bits(SrcReg1, effectiveShift - 1)) {
- ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit));
+ cfofBits = cfofBits | (ext & CFBit);
+ ecfBit = ecfBit | (ext & ECFBit);
}
+
//Use the regular mechanisms to calculate the other flags.
- ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit |
OFBit),
- DestReg, psrc1, op2);
+ uint64_t newFlags = genFlags(ccFlagBits | ezfBit,
+ ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2);
+ ezfBit = newFlags & EZFBit;
+ ccFlagBits = newFlags & ccFlagMask;
}
'''
@@ -797,19 +839,27 @@
if (shiftAmt) {
//Zero out any flags we might modify. This way we only have to
//worry about setting them.
- ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit));
+ cfofBits = cfofBits & ~(ext & (CFBit | OFBit));
+ ecfBit = ecfBit & ~(ext & ECFBit);
+
//Find the most and second most significant bits of the result.
int msb = bits(DestReg, dataSize * 8 - 1);
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