changeset afa278317136 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=afa278317136
description:
X86 Regression: update stats due to cc register split
diffstat:
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
| 12 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
| 1498 +++++-----
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
| 2 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
| 6 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
| 34 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
| 10 +-
tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
| 18 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
| 895 ++--
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
| 2 +-
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
| 14 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
| 2 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
| 14 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
| 13 +-
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
| 919 +++---
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
| 14 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
| 14 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
| 37 +-
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
| 957 +++---
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
| 14 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
| 4 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
| 14 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
| 2 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
| 14 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
| 2 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
| 14 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
| 10 +-
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
| 867 ++--
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
| 2 +-
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
| 14 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
| 2 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
| 8 +-
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
| 14 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
| 14 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
| 6 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
| 10 +-
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
| 14 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
| 10 +-
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
| 675 ++--
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
| 12 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
| 30 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
| 14 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
| 2 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
| 8 +-
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
| 12 +-
69 files changed, 3224 insertions(+), 3175 deletions(-)
diffs (truncated from 8056 to 300 lines):
diff -r 6d64aa6a26af -r afa278317136
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini Tue May
22 11:35:58 2012 -0500
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini Tue May
22 11:38:04 2012 -0500
@@ -15,7 +15,7 @@
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
@@ -1263,7 +1263,7 @@
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
@@ -1283,7 +1283,7 @@
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/dist/m5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
diff -r 6d64aa6a26af -r afa278317136
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout Tue May
22 11:35:58 2012 -0500
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout Tue May
22 11:38:04 2012 -0500
@@ -1,13 +1,15 @@
+Redirecting stdout to
build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
+Redirecting stderr to
build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled May 8 2012 15:05:30
-gem5 started May 8 2012 16:05:33
-gem5 executing on piton
+gem5 compiled May 21 2012 19:00:49
+gem5 started May 21 2012 19:00:58
+gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d
build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re
tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at:
/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5169499540500 because m5_exit instruction encountered
+Exiting @ tick 5157514159500 because m5_exit instruction encountered
diff -r 6d64aa6a26af -r afa278317136
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt Tue May
22 11:35:58 2012 -0500
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt Tue May
22 11:38:04 2012 -0500
@@ -1,151 +1,151 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 5.169500 #
Number of seconds simulated
-sim_ticks 5169499540500 #
Number of ticks simulated
-final_tick 5169499540500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
+sim_seconds 5.157514 #
Number of seconds simulated
+sim_ticks 5157514159500 #
Number of ticks simulated
+final_tick 5157514159500 #
Number of ticks from beginning of simulation (restored from checkpoints and
never reset)
sim_freq 1000000000000 #
Frequency of simulated ticks
-host_inst_rate 77808 #
Simulator instruction rate (inst/s)
-host_op_rate 153328 #
Simulator op (including micro ops) rate (op/s)
-host_tick_rate 943017240 #
Simulator tick rate (ticks/s)
-host_mem_usage 366644 #
Number of bytes of host memory used
-host_seconds 5481.87 #
Real time elapsed on the host
-sim_insts 426530860 #
Number of instructions simulated
-sim_ops 840523890 #
Number of ops (including micro ops) simulated
-system.physmem.bytes_read 15909184 #
Number of bytes read from this memory
-system.physmem.bytes_inst_read 1237824 #
Number of instructions bytes read from this memory
-system.physmem.bytes_written 12067392 #
Number of bytes written to this memory
-system.physmem.num_reads 248581 #
Number of read requests responded to by this memory
-system.physmem.num_writes 188553 #
Number of write requests responded to by this memory
+host_inst_rate 88188 #
Simulator instruction rate (inst/s)
+host_op_rate 173786 #
Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1066411603 #
Simulator tick rate (ticks/s)
+host_mem_usage 415716 #
Number of bytes of host memory used
+host_seconds 4836.33 #
Real time elapsed on the host
+sim_insts 426506235 #
Number of instructions simulated
+sim_ops 840483958 #
Number of ops (including micro ops) simulated
+system.physmem.bytes_read 15959488 #
Number of bytes read from this memory
+system.physmem.bytes_inst_read 1257664 #
Number of instructions bytes read from this memory
+system.physmem.bytes_written 12050112 #
Number of bytes written to this memory
+system.physmem.num_reads 249367 #
Number of read requests responded to by this memory
+system.physmem.num_writes 188283 #
Number of write requests responded to by this memory
system.physmem.num_other 0 #
Number of other requests responded to by this memory
-system.physmem.bw_read 3077510 #
Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 239448 #
Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 2334344 #
Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 5411854 #
Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 167476 #
number of replacements
-system.l2c.tagsinuse 37831.311454 #
Cycle average of tags in use
-system.l2c.total_refs 3834095 #
Total number of references to valid blocks.
-system.l2c.sampled_refs 201653 #
Sample count of references to valid blocks.
-system.l2c.avg_refs 19.013330 #
Average number of references to valid blocks.
+system.physmem.bw_read 3094415 #
Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read 243851 #
Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write 2336419 #
Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total 5430833 #
Total bandwidth to/from this memory (bytes/s)
+system.l2c.replacements 167142 #
number of replacements
+system.l2c.tagsinuse 37816.689690 #
Cycle average of tags in use
+system.l2c.total_refs 3843284 #
Total number of references to valid blocks.
+system.l2c.sampled_refs 202399 #
Sample count of references to valid blocks.
+system.l2c.avg_refs 18.988651 #
Average number of references to valid blocks.
system.l2c.warmup_cycle 0 #
Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::writebacks 26693.996125 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.dtb.walker 11.281842 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.itb.walker 0.035682 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.inst 2446.646461 #
Average occupied blocks per requestor
-system.l2c.occ_blocks::cpu.data 8679.351345 #
Average occupied blocks per requestor
-system.l2c.occ_percent::writebacks 0.407318 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.dtb.walker 0.000172 #
Average percentage of cache occupancy
+system.l2c.occ_blocks::writebacks 26702.073389 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 8.025761 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 0.043125 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 2426.285000 #
Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 8680.262415 #
Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.407441 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker 0.000122 #
Average percentage of cache occupancy
system.l2c.occ_percent::cpu.itb.walker 0.000001 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.inst 0.037333 #
Average percentage of cache occupancy
-system.l2c.occ_percent::cpu.data 0.132436 #
Average percentage of cache occupancy
-system.l2c.occ_percent::total 0.577260 #
Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu.dtb.walker 109979 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.itb.walker 9264 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.inst 1065061 #
number of ReadReq hits
-system.l2c.ReadReq_hits::cpu.data 1335148 #
number of ReadReq hits
-system.l2c.ReadReq_hits::total 2519452 #
number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 1598542 #
number of Writeback hits
-system.l2c.Writeback_hits::total 1598542 #
number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu.data 324 #
number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 324 #
number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu.data 151430 #
number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 151430 #
number of ReadExReq hits
-system.l2c.demand_hits::cpu.dtb.walker 109979 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu.itb.walker 9264 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu.inst 1065061 #
number of demand (read+write) hits
-system.l2c.demand_hits::cpu.data 1486578 #
number of demand (read+write) hits
-system.l2c.demand_hits::total 2670882 #
number of demand (read+write) hits
-system.l2c.overall_hits::cpu.dtb.walker 109979 #
number of overall hits
-system.l2c.overall_hits::cpu.itb.walker 9264 #
number of overall hits
-system.l2c.overall_hits::cpu.inst 1065061 #
number of overall hits
-system.l2c.overall_hits::cpu.data 1486578 #
number of overall hits
-system.l2c.overall_hits::total 2670882 #
number of overall hits
-system.l2c.ReadReq_misses::cpu.dtb.walker 104 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.itb.walker 11 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.inst 19342 #
number of ReadReq misses
-system.l2c.ReadReq_misses::cpu.data 45291 #
number of ReadReq misses
-system.l2c.ReadReq_misses::total 64748 #
number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu.data 2653 #
number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2653 #
number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu.data 141019 #
number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 141019 #
number of ReadExReq misses
-system.l2c.demand_misses::cpu.dtb.walker 104 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu.itb.walker 11 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu.inst 19342 #
number of demand (read+write) misses
-system.l2c.demand_misses::cpu.data 186310 #
number of demand (read+write) misses
-system.l2c.demand_misses::total 205767 #
number of demand (read+write) misses
-system.l2c.overall_misses::cpu.dtb.walker 104 #
number of overall misses
-system.l2c.overall_misses::cpu.itb.walker 11 #
number of overall misses
-system.l2c.overall_misses::cpu.inst 19342 #
number of overall misses
-system.l2c.overall_misses::cpu.data 186310 #
number of overall misses
-system.l2c.overall_misses::total 205767 #
number of overall misses
-system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5428000
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.itb.walker 573500
# number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.inst 1010710500 #
number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu.data 2380797000 #
number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 3397509000 #
number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu.data 37026000
# number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 37026000 #
number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu.data 7343771000
# number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7343771000 #
number of ReadExReq miss cycles
-system.l2c.demand_miss_latency::cpu.dtb.walker 5428000
# number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.itb.walker 573500
# number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.inst 1010710500 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu.data 9724568000 #
number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 10741280000 #
number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu.dtb.walker 5428000
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.itb.walker 573500
# number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.inst 1010710500 #
number of overall miss cycles
-system.l2c.overall_miss_latency::cpu.data 9724568000 #
number of overall miss cycles
-system.l2c.overall_miss_latency::total 10741280000 #
number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu.dtb.walker 110083
# number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.itb.walker 9275
# number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.inst 1084403 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu.data 1380439 #
number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2584200 #
number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 1598542 #
number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 1598542 #
number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu.data 2977 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2977 #
number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu.data 292449 #
number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 292449 #
number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu.dtb.walker 110083
# number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.itb.walker 9275
# number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.inst 1084403 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu.data 1672888 #
number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2876649 #
number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu.dtb.walker 110083
# number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.itb.walker 9275
# number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.inst 1084403 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu.data 1672888 #
number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2876649 #
number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000945
# miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001186
# miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.inst 0.017837 #
miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu.data 0.032809 #
miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu.data 0.891166 #
miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu.data 0.482200 #
miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu.dtb.walker 0.000945
# miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.itb.walker 0.001186
# miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.inst 0.017837 #
miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu.data 0.111370 #
miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu.dtb.walker 0.000945
# miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.itb.walker 0.001186
# miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.inst 0.017837 #
miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu.data 0.111370 #
miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52192.307692
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52136.363636
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.inst 52254.704788
# average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu.data 52566.668875
# average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu.data 13956.275914
# average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu.data 52076.464874
# average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52192.307692
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.itb.walker 52136.363636
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.inst 52254.704788
# average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu.data 52195.630938
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52192.307692
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.itb.walker 52136.363636
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.inst 52254.704788
# average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu.data 52195.630938
# average overall miss latency
+system.l2c.occ_percent::cpu.inst 0.037022 #
Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.132450 #
Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.577037 #
Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 109565 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 8804 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 1063948 #
number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 1334758 #
number of ReadReq hits
+system.l2c.ReadReq_hits::total 2517075 #
number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 1600724 #
number of Writeback hits
+system.l2c.Writeback_hits::total 1600724 #
number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu.data 336 #
number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 336 #
number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu.data 151728 #
number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 151728 #
number of ReadExReq hits
+system.l2c.demand_hits::cpu.dtb.walker 109565 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker 8804 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst 1063948 #
number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 1486486 #
number of demand (read+write) hits
+system.l2c.demand_hits::total 2668803 #
number of demand (read+write) hits
+system.l2c.overall_hits::cpu.dtb.walker 109565 #
number of overall hits
+system.l2c.overall_hits::cpu.itb.walker 8804 #
number of overall hits
+system.l2c.overall_hits::cpu.inst 1063948 #
number of overall hits
+system.l2c.overall_hits::cpu.data 1486486 #
number of overall hits
+system.l2c.overall_hits::total 2668803 #
number of overall hits
+system.l2c.ReadReq_misses::cpu.dtb.walker 105 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker 17 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 19652 #
number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 45660 #
number of ReadReq misses
+system.l2c.ReadReq_misses::total 65434 #
number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu.data 2521 #
number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2521 #
number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu.data 141129 #
number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 141129 #
number of ReadExReq misses
+system.l2c.demand_misses::cpu.dtb.walker 105 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker 17 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst 19652 #
number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data 186789 #
number of demand (read+write) misses
+system.l2c.demand_misses::total 206563 #
number of demand (read+write) misses
+system.l2c.overall_misses::cpu.dtb.walker 105 #
number of overall misses
+system.l2c.overall_misses::cpu.itb.walker 17 #
number of overall misses
+system.l2c.overall_misses::cpu.inst 19652 #
number of overall misses
+system.l2c.overall_misses::cpu.data 186789 #
number of overall misses
+system.l2c.overall_misses::total 206563 #
number of overall misses
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker 5480500
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker 886000
# number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst 1027000000 #
number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data 2399872000 #
number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 3433238500 #
number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data 39054500
# number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 39054500 #
number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data 7349617000
# number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7349617000 #
number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker 5480500
# number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker 886000
# number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst 1027000000 #
number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data 9749489000 #
number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 10782855500 #
number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker 5480500
# number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker 886000
# number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst 1027000000 #
number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data 9749489000 #
number of overall miss cycles
+system.l2c.overall_miss_latency::total 10782855500 #
number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker 109670
# number of ReadReq accesses(hits+misses)
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