changeset a1104cc13db2 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=a1104cc13db2
description:
O3: Clean up the O3 structures and try to pack them a bit better.
DynInst is extremely large the hope is that this re-organization will
put the
most used members close to each other.
diffstat:
src/arch/alpha/registers.hh | 3 +
src/arch/arm/registers.hh | 1 +
src/arch/isa_parser.py | 8 +
src/arch/mips/registers.hh | 1 +
src/arch/power/registers.hh | 1 +
src/arch/sparc/registers.hh | 1 +
src/arch/x86/registers.hh | 1 +
src/cpu/base_dyn_inst.hh | 437 +++++++++++++++++++++--------------------
src/cpu/base_dyn_inst_impl.hh | 22 +-
src/cpu/o3/bpred_unit.hh | 17 +-
src/cpu/o3/comm.hh | 27 +-
src/cpu/o3/commit_impl.hh | 10 +-
src/cpu/o3/decode_impl.hh | 2 +-
src/cpu/o3/dyn_inst.hh | 23 +-
src/cpu/o3/dyn_inst_impl.hh | 3 +-
src/cpu/o3/iew_impl.hh | 4 +-
src/cpu/o3/inst_queue_impl.hh | 20 +-
src/cpu/o3/lsq_unit.hh | 35 +-
src/cpu/o3/lsq_unit_impl.hh | 18 +-
src/cpu/o3/rename_impl.hh | 4 +-
20 files changed, 320 insertions(+), 318 deletions(-)
diffs (truncated from 1295 to 300 lines):
diff -r eb2975c014cd -r a1104cc13db2 src/arch/alpha/registers.hh
--- a/src/arch/alpha/registers.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/alpha/registers.hh Tue Jun 05 01:23:09 2012 -0400
@@ -40,6 +40,9 @@
using AlphaISAInst::MaxInstSrcRegs;
using AlphaISAInst::MaxInstDestRegs;
+// Locked read/write flags are can't be detected by the ISA parser
+const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
+
typedef uint8_t RegIndex;
typedef uint64_t IntReg;
diff -r eb2975c014cd -r a1104cc13db2 src/arch/arm/registers.hh
--- a/src/arch/arm/registers.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/arm/registers.hh Tue Jun 05 01:23:09 2012 -0400
@@ -55,6 +55,7 @@
const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
ArmISAInst::MaxInstSrcRegs;
using ArmISAInst::MaxInstDestRegs;
+using ArmISAInst::MaxMiscDestRegs;
typedef uint16_t RegIndex;
diff -r eb2975c014cd -r a1104cc13db2 src/arch/isa_parser.py
--- a/src/arch/isa_parser.py Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/isa_parser.py Tue Jun 05 01:23:09 2012 -0400
@@ -726,6 +726,7 @@
self.numDestRegs = 0
self.numFPDestRegs = 0
self.numIntDestRegs = 0
+ self.numMiscDestRegs = 0
self.memOperand = None
for op_desc in self.items:
if op_desc.isReg():
@@ -739,6 +740,8 @@
self.numFPDestRegs += 1
elif op_desc.isIntReg():
self.numIntDestRegs += 1
+ elif op_desc.isControlReg():
+ self.numMiscDestRegs += 1
elif op_desc.isMem():
if self.memOperand:
error("Code block has more than one memory operand.")
@@ -747,6 +750,8 @@
parser.maxInstSrcRegs = self.numSrcRegs
if parser.maxInstDestRegs < self.numDestRegs:
parser.maxInstDestRegs = self.numDestRegs
+ if parser.maxMiscDestRegs < self.numMiscDestRegs:
+ parser.maxMiscDestRegs = self.numMiscDestRegs
# now make a final pass to finalize op_desc fields that may depend
# on the register enumeration
for op_desc in self.items:
@@ -1001,6 +1006,7 @@
const int MaxInstSrcRegs = %(MaxInstSrcRegs)d;
const int MaxInstDestRegs = %(MaxInstDestRegs)d;
+ const int MaxMiscDestRegs = %(MaxMiscDestRegs)d;
} // namespace %(namespace)s
@@ -1036,6 +1042,7 @@
self.maxInstSrcRegs = 0
self.maxInstDestRegs = 0
+ self.maxMiscDestRegs = 0
#####################################################################
#
@@ -1990,6 +1997,7 @@
# value of the globals.
MaxInstSrcRegs = self.maxInstSrcRegs
MaxInstDestRegs = self.maxInstDestRegs
+ MaxMiscDestRegs = self.maxMiscDestRegs
# max_inst_regs.hh
self.update_if_needed('max_inst_regs.hh',
max_inst_regs_template % vars())
diff -r eb2975c014cd -r a1104cc13db2 src/arch/mips/registers.hh
--- a/src/arch/mips/registers.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/mips/registers.hh Tue Jun 05 01:23:09 2012 -0400
@@ -43,6 +43,7 @@
using MipsISAInst::MaxInstSrcRegs;
using MipsISAInst::MaxInstDestRegs;
+using MipsISAInst::MaxMiscDestRegs;
// Constants Related to the number of registers
const int NumIntArchRegs = 32;
diff -r eb2975c014cd -r a1104cc13db2 src/arch/power/registers.hh
--- a/src/arch/power/registers.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/power/registers.hh Tue Jun 05 01:23:09 2012 -0400
@@ -38,6 +38,7 @@
using PowerISAInst::MaxInstSrcRegs;
using PowerISAInst::MaxInstDestRegs;
+using PowerISAInst::MaxMiscDestRegs;
typedef uint8_t RegIndex;
diff -r eb2975c014cd -r a1104cc13db2 src/arch/sparc/registers.hh
--- a/src/arch/sparc/registers.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/sparc/registers.hh Tue Jun 05 01:23:09 2012 -0400
@@ -42,6 +42,7 @@
using SparcISAInst::MaxInstSrcRegs;
using SparcISAInst::MaxInstDestRegs;
+using SparcISAInst::MaxMiscDestRegs;
typedef uint64_t IntReg;
typedef uint64_t MiscReg;
diff -r eb2975c014cd -r a1104cc13db2 src/arch/x86/registers.hh
--- a/src/arch/x86/registers.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/arch/x86/registers.hh Tue Jun 05 01:23:09 2012 -0400
@@ -49,6 +49,7 @@
{
using X86ISAInst::MaxInstSrcRegs;
using X86ISAInst::MaxInstDestRegs;
+using X86ISAInst::MaxMiscDestRegs;
const int NumMiscArchRegs = NUM_MISCREGS;
const int NumMiscRegs = NUM_MISCREGS;
diff -r eb2975c014cd -r a1104cc13db2 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Tue Jun 05 01:23:09 2012 -0400
+++ b/src/cpu/base_dyn_inst.hh Tue Jun 05 01:23:09 2012 -0400
@@ -98,17 +98,202 @@
MaxInstDestRegs = TheISA::MaxInstDestRegs /// Max dest regs
};
+ union Result {
+ uint64_t integer;
+ double dbl;
+ void set(uint64_t i) { integer = i; }
+ void set(double d) { dbl = d; }
+ void get(uint64_t& i) { i = integer; }
+ void get(double& d) { d = dbl; }
+ };
+
+ protected:
+ enum Status {
+ IqEntry, /// Instruction is in the IQ
+ RobEntry, /// Instruction is in the ROB
+ LsqEntry, /// Instruction is in the LSQ
+ Completed, /// Instruction has completed
+ ResultReady, /// Instruction has its result
+ CanIssue, /// Instruction can issue and execute
+ Issued, /// Instruction has issued
+ Executed, /// Instruction has executed
+ CanCommit, /// Instruction can commit
+ AtCommit, /// Instruction has reached commit
+ Committed, /// Instruction has committed
+ Squashed, /// Instruction is squashed
+ SquashedInIQ, /// Instruction is squashed in the IQ
+ SquashedInLSQ, /// Instruction is squashed in the LSQ
+ SquashedInROB, /// Instruction is squashed in the ROB
+ RecoverInst, /// Is a recover instruction
+ BlockingInst, /// Is a blocking instruction
+ ThreadsyncWait, /// Is a thread synchronization instruction
+ SerializeBefore, /// Needs to serialize on
+ /// instructions ahead of it
+ SerializeAfter, /// Needs to serialize instructions behind it
+ SerializeHandled, /// Serialization has been handled
+ NumStatus
+ };
+
+ enum Flags {
+ TranslationStarted,
+ TranslationCompleted,
+ PossibleLoadViolation,
+ HitExternalSnoop,
+ EffAddrValid,
+ RecordResult,
+ Predicate,
+ PredTaken,
+ /** Whether or not the effective address calculation is completed.
+ * @todo: Consider if this is necessary or not.
+ */
+ EACalcDone,
+ IsUncacheable,
+ ReqMade,
+ MemOpDone,
+ MaxFlags
+ };
+
+ public:
+ /** The sequence number of the instruction. */
+ InstSeqNum seqNum;
+
/** The StaticInst used by this BaseDynInst. */
StaticInstPtr staticInst;
+
+ /** Pointer to the Impl's CPU object. */
+ ImplCPU *cpu;
+
+ /** Pointer to the thread state. */
+ ImplState *thread;
+
+ /** The kind of fault this instruction has generated. */
+ Fault fault;
+
+ /** InstRecord that tracks this instructions. */
+ Trace::InstRecord *traceData;
+
+ protected:
+ /** The result of the instruction; assumes an instruction can have many
+ * destination registers.
+ */
+ std::queue<Result> instResult;
+
+ /** PC state for this instruction. */
+ TheISA::PCState pc;
+
+ /* An amalgamation of a lot of boolean values into one */
+ std::bitset<MaxFlags> instFlags;
+
+ /** The status of this BaseDynInst. Several bits can be set. */
+ std::bitset<NumStatus> status;
+
+ /** Whether or not the source register is ready.
+ * @todo: Not sure this should be here vs the derived class.
+ */
+ std::bitset<MaxInstSrcRegs> _readySrcRegIdx;
+
+ public:
+ /** The thread this instruction is from. */
+ ThreadID threadNumber;
+
+ /** Iterator pointing to this BaseDynInst in the list of all insts. */
+ ListIt instListIt;
+
+ ////////////////////// Branch Data ///////////////
+ /** Predicted PC state after this instruction. */
+ TheISA::PCState predPC;
+
+ /** The Macroop if one exists */
StaticInstPtr macroop;
+ /** How many source registers are ready. */
+ uint8_t readyRegs;
+
+ public:
+ /////////////////////// Load Store Data //////////////////////
+ /** The effective virtual address (lds & stores only). */
+ Addr effAddr;
+
+ /** The effective physical address. */
+ Addr physEffAddr;
+
+ /** The memory request flags (from translation). */
+ unsigned memReqFlags;
+
+ /** data address space ID, for loads & stores. */
+ short asid;
+
+ /** The size of the request */
+ uint8_t effSize;
+
+ /** Pointer to the data for the memory access. */
+ uint8_t *memData;
+
+ /** Load queue index. */
+ int16_t lqIdx;
+
+ /** Store queue index. */
+ int16_t sqIdx;
+
+
+ /////////////////////// TLB Miss //////////////////////
+ /**
+ * Saved memory requests (needed when the DTB address translation is
+ * delayed due to a hw page table walk).
+ */
+ RequestPtr savedReq;
+ RequestPtr savedSreqLow;
+ RequestPtr savedSreqHigh;
+
+ /////////////////////// Checker //////////////////////
+ // Need a copy of main request pointer to verify on writes.
+ RequestPtr reqToVerify;
+
+ private:
+ /** Instruction effective address.
+ * @todo: Consider if this is necessary or not.
+ */
+ Addr instEffAddr;
+
+ protected:
+ /** Flattened register index of the destination registers of this
+ * instruction.
+ */
+ TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
+
+ /** Physical register index of the destination registers of this
+ * instruction.
+ */
+ PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
+
+ /** Physical register index of the source registers of this
+ * instruction.
+ */
+ PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
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