changeset 1554b7722990 in /z/repo/gem5
details: http://repo.gem5.org/gem5?cmd=changeset;node=1554b7722990
description:
ARM: removed extra white space
Extra white space fixes in miscregs.hh
diffstat:
src/arch/arm/miscregs.hh | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diffs (25 lines):
diff -r ed4378739b6e -r 1554b7722990 src/arch/arm/miscregs.hh
--- a/src/arch/arm/miscregs.hh Tue Jun 05 01:23:10 2012 -0400
+++ b/src/arch/arm/miscregs.hh Tue Jun 05 01:23:10 2012 -0400
@@ -351,7 +351,7 @@
Bitfield<31> ie; // Instruction endianness
Bitfield<30> te; // Thumb Exception Enable
Bitfield<29> afe; // Access flag enable
- Bitfield<28> tre; // TEX Remap bit
+ Bitfield<28> tre; // TEX Remap bit
Bitfield<27> nmfi;// Non-maskable fast interrupts enable
Bitfield<25> ee; // Exception Endianness bit
Bitfield<24> ve; // Interrupt vectors enable
@@ -369,10 +369,10 @@
Bitfield<10> sw; // Enable swp/swpb
Bitfield<9,8> rs; // deprecated protection bits
Bitfield<6,3> rao4;// Read as one
- Bitfield<7> b; // Endianness support (unused)
+ Bitfield<7> b; // Endianness support (unused)
Bitfield<2> c; // Cache enable bit
Bitfield<1> a; // Alignment fault checking
- Bitfield<0> m; // MMU enable bit
+ Bitfield<0> m; // MMU enable bit
EndBitUnion(SCTLR)
BitUnion32(CPACR)
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