> On June 5, 2012, 11:10 a.m., Ali Saidi wrote:
> > Are you still working on this?
> >
>
> Anthony Gutierrez wrote:
> Yes. I took a break to get ICS working with BBench.
>
> But, it switches back-and-forth between O3CPUs for a while now. My latest
> problem is that while the CPU is "draining" the exit event is the next thing
> scheduled. The simulator exits and the following assert fails:
> cleanupCountedDrain(Event*): Assertion `event->getCount() == 0'. The only
> object yet to drain is the CPU. I can send more details about the problems to
> the mailing list.
>
> Ali Saidi wrote:
> Did it go negative or is it still positive? If it went negative someone
> thought they were drained twice. I'm not sure how it could happen that it is
> positive.
>
It's equal to 1, the CPU object hasn't drained. The simulator stops making
progress here:
11064054500: system.cpu + A0 T0 : @die+32 : bl :
IntAlu : D=0x00000000c0036768 FetchSeq=6182727 CPSeq=5938002
11064058000: system.cpu + A0 T0 : @_raw_spin_lock_irq : cps #64
: IntAlu : D=0x00000000000001d3 FetchSeq=6182734 CPSeq=5938003
11064058000: system.cpu + A0 T0 : @_raw_spin_lock_irq+4 : mov r3, #1
: IntAlu : D=0x0000000000000001 FetchSeq=6182735 CPSeq=5938004
11064058000: system.cpu + A0 T0 : @_raw_spin_lock_irq+8 : ldrex r2, [r0,
#0] : MemRead : D=0x0000000000000001 A=0xc040e2f0 FetchSeq=6182736
CPSeq=5938005
11064058500: system.cpu + A0 T0 : @_raw_spin_lock_irq+12 : teqs r2, #0
: IntAlu : D=0x0000000000000000 FetchSeq=6182737 CPSeq=5938006
11064058500: system.cpu + A0 T0 : @_raw_spin_lock_irq+16 : wfene
: IntAlu : D=0x0000000000000000 FetchSeq=6182738 CPSeq=5938007
11064058500: system.cpu + A0 T0 : @_raw_spin_lock_irq+20 : strexeq r2,
r3, [r0, #0] : MemWrite : Predicated False FetchSeq=6182739 CPSeq=5938008
11064109500: system.cpu + A0 T0 : @_raw_spin_lock_irq+24 : teqseq r2, #0
: IntAlu : Predicated False FetchSeq=6182740 CPSeq=5938009
11064109500: system.cpu + A0 T0 : @_raw_spin_lock_irq+28 : bne
: IntAlu : FetchSeq=6182741 CPSeq=5938010
11064117500: system.cpu + A0 T0 : @_raw_spin_lock_irq+8 : ldrex r2, [r0,
#0] : MemRead : D=0x0000000000000001 A=0xc040e2f0 FetchSeq=6182752
CPSeq=5938011
11064117500: system.cpu + A0 T0 : @_raw_spin_lock_irq+12 : teqs r2, #0
: IntAlu : D=0x0000000000000000 FetchSeq=6182753 CPSeq=5938012
The next instruction is a wfene, it is stuck at the top of the ROB and can't
commit. Also, the kernel panics slightly before it starts spinning on that
lock, as you can see.
- Anthony
-----------------------------------------------------------
This is an automatically generated e-mail. To reply, visit:
http://reviews.gem5.org/r/1221/#review2907
-----------------------------------------------------------
On May 26, 2012, 8:50 a.m., Anthony Gutierrez wrote:
>
> -----------------------------------------------------------
> This is an automatically generated e-mail. To reply, visit:
> http://reviews.gem5.org/r/1221/
> -----------------------------------------------------------
>
> (Updated May 26, 2012, 8:50 a.m.)
>
>
> Review request for Default.
>
>
> Description
> -------
>
> Changeset 9023:bf655276f847
> ---------------------------
> O3,ARM: This patch fixes some problems with the drain/switchout functionality
> for the O3 cpu and for the ARM ISA. This is an incremental fix as there are
> still a few bugs/mem leaks with the switchout code. Particularly when
> switching from an O3CPU to a TimingSimpleCPU. This patch fixes: i/d cache and
> i/d TLB port re-connections when switcing out, draining of the ARM
> TableWalker, and commit stage draining in the O3 CPU.
>
>
> Diffs
> -----
>
> src/arch/arm/table_walker.hh bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/arch/arm/table_walker.cc bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/cpu/base.cc bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/cpu/o3/commit_impl.hh bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/cpu/o3/cpu.cc bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/cpu/o3/fetch_impl.hh bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/cpu/o3/iew.hh bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/dev/dma_device.cc bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/mem/packet_queue.cc bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/mem/port.hh bb25e7646c41469bef2b78ba435319f59d63d5fd
> src/mem/port.cc bb25e7646c41469bef2b78ba435319f59d63d5fd
>
> Diff: http://reviews.gem5.org/r/1221/diff/
>
>
> Testing
> -------
>
>
> Thanks,
>
> Anthony Gutierrez
>
>
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