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Looks good to me except the one comment below. src/mem/ruby/system/Cache.py <http://reviews.gem5.org/r/1291/#comment3230> I think this should default to false here. Unless people take serious consideration of the number of banks and latencies the timing results won't make any sense. - Jason Power On July 2, 2012, 10:42 p.m., Brad Beckmann wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1291/ > ----------------------------------------------------------- > > (Updated July 2, 2012, 10:42 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9079:02a69df7533b > --------------------------- > ruby: banked cache array resource model > > This patch models a cache as separate tag and data arrays. The patch exposes > the banked array as another resource that is checked by SLICC before a > transition is allowed to execute. This is similar to how TBE entries and > slots > in output ports are modeled. > > > Diffs > ----- > > src/mem/SConscript d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/protocol/RubySlicc_Exports.sm > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/protocol/RubySlicc_Types.sm > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/BankedArray.hh PRE-CREATION > src/mem/ruby/system/BankedArray.cc PRE-CREATION > src/mem/ruby/system/Cache.py d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/CacheMemory.hh d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/CacheMemory.cc d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/SConscript d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/symbols/StateMachine.py > d8e5ca139d7c24eeb665ac0aab41e180886278cb > > Diff: http://reviews.gem5.org/r/1291/diff/ > > > Testing > ------- > > > Thanks, > > Brad Beckmann > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
