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(Updated July 3, 2012, 2:51 p.m.) Review request for Default. Description (updated) ------- Changeset 9087:920818736f19 --------------------------- ARM: fix value of MISCREG_CTR returned by readMiscReg() According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines) [31:29] Format - b100 specifies v7 [28] RAZ - b0 [27:24] CWG log2(max writeback size #words) - 0x4 16 words [23:20] ERG log2(max reservation size #words) - 0x4 16 words [19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words [15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT [13:4] RAZ - b0000000000 [3:0] IminLine log2(smallest icache line #words) - 0x4 16 words Diffs (updated) ----- src/arch/arm/isa.cc 5f0321c03a2602f34dd03700e41e0cf5b47b8761 src/arch/arm/miscregs.hh 5f0321c03a2602f34dd03700e41e0cf5b47b8761 Diff: http://reviews.gem5.org/r/1117/diff/ Testing ------- Ran BBench with the mcr icimvau instruction implemented. There is kernel code that relies on the proper implementation of this register when performing cache maintenance operations see arch/arm/mm/cache-v7.S in the linux kernel source. Thanks, Anthony Gutierrez _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
