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Ship it! Does this require changes to the protocol to collect the statistics? If I'm right, I assume you considered ways to collect the statistics more automatically/implicitly and rejected them... - Steve Reinhardt On July 2, 2012, 10:43 p.m., Brad Beckmann wrote: > > ----------------------------------------------------------- > This is an automatically generated e-mail. To reply, visit: > http://reviews.gem5.org/r/1290/ > ----------------------------------------------------------- > > (Updated July 2, 2012, 10:43 p.m.) > > > Review request for Default. > > > Description > ------- > > Changeset 9078:c2c677534b91 > --------------------------- > ruby: tag and data cache access support > > Updates to Ruby to support statistics counting of cache accesses. This > feature > serves multiple purposes beyond simple stats collection. It provides the > foundation for ruby to model the cache tag and data arrays as physical > resources, as well as provide the necessary input data for McPAT power > modeling. > > > Diffs > ----- > > src/mem/SConscript d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/protocol/RubySlicc_Exports.sm > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/protocol/RubySlicc_Types.sm > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/CacheMemory.hh d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/CacheMemory.cc d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/DMASequencer.hh > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/DMASequencer.cc > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/DirectoryMemory.hh > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/DirectoryMemory.cc > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/MemoryControl.hh > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/MemoryControl.cc > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/Sequencer.hh d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/ruby/system/Sequencer.cc d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/ast/TransitionDeclAST.py > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/ast/TypeFieldEnumAST.py > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/parser.py d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/symbols/StateMachine.py > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/symbols/Statistic.py PRE-CREATION > src/mem/slicc/symbols/Transition.py > d8e5ca139d7c24eeb665ac0aab41e180886278cb > src/mem/slicc/symbols/__init__.py d8e5ca139d7c24eeb665ac0aab41e180886278cb > > Diff: http://reviews.gem5.org/r/1290/diff/ > > > Testing > ------- > > > Thanks, > > Brad Beckmann > > _______________________________________________ gem5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/gem5-dev
